SMJ320C31_07 Datasheet, PDF (22/59 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
memory read / write timing (continued)
H3
H1
13
12
STRB
20
14
R/W
15
23
A
21
22
D
19
18
RDY
Figure 15. Timing for Memory (STRB = 0) Write
Address-Bus Timing Variation Load Capacitance
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
Change in Load Capacitance, pF
NOTE A: 30 pF/ns slope
Figure 16. Address-Bus Timing Variation With Load Capacitance (see Note A)
22
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