DS90UB914ATRHSTQ1 Datasheet, PDF (7/68 Pages) Texas Instruments – DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit

DS90UB913A-Q1, DS90UB914A-Q1
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Pin Name
Pin No.
RIN1-
33
RES
43,44
CMLOUTP/N
38,39
POWER AND GROUND
VDDIO1/2/3
29, 20, 7
VDDD
VDDSSCG
VDDR
VDDCML0/1
VDDPLL
17
3
36
40,31
45
VSS
DAP
SNLS443A – MAY 2013 – REVISED JUNE 2013
Table 2. Pin Descriptions (continued)
I/O, Type
Input/Output,
CML
—
Description
Inverting Differential input, bidirectional control channel. The IO must be AC coupled
with a 0.1µF capacitor. For applications using single-ended coaxial interconnect,
terminate to Ground with a 0.047µF capacitor.
Reserved. This pin must always be tied low.
Route to test point or leave open if unused.
Power, Digital
Power, Digital
Power, Analog
Power, Analog
Power, Analog
Power, Analog
Ground, DAP
LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered
from V_DDIO. V_DDIO can be connected to a 1.8V ±5% or 3.3V ±10%.
Digital Core Power, 1.8V ±5%.
SSCG PLL Power, 1.8V ±5%.
Rx Analog Power, 1.8V ±5%.
CML and Bidirectional control channel Drive Power, 1.8V±5%.
PLL Power, 1.8V ±5%.
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
the center of the WQFN package. Connected to the ground plane (GND) with at least
16 vias.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2013, Texas Instruments Incorporated
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