DS90UB914ATRHSTQ1 Datasheet, PDF (41/68 Pages) Texas Instruments – DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit

DS90UB913A-Q1, DS90UB914A-Q1
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FUNCTIONAL DESCRIPTION
SNLS443A – MAY 2013 – REVISED JUNE 2013
The DS90UB913A-Q1 is optimized to interface with the DS90UB914A-Q1 using a 50Ω coax interface. The
DS90UB913A-Q1 will also work with the DS90UB914A-Q1 using an STP interface.
The DS90UB913A/914A FPD- Link III chipsets are intended to link mega-pixel camera imagers and video
processors in ECUs. The Serializer/Deserializer chipset can operate from 25 MHz to 100 MHz pixel clock
frequency. The DS90UB913A-Q1 device transforms a 10/12-bit wide parallel LVCMOS data bus along with a
bidirectional control channel control bus into a single high-speed differential pair. The high speed serial bit stream
contains an embedded clock and DC-balanced information which enhances signal quality to support AC
coupling. The DS90UB914A-Q1 device receives the single serial data stream and converts it back into a 10/12-
bit wide parallel data bus together with the control channel data bus. The DS90UB913A/914A chipsets can
accept up to:
■ 12-bits of DATA + 2 bits SYNC for an input PCLK range of 25 MHz to 50 MHz in the 12-bit low frequency
mode. Note: No HS/VS restrictions (raw).
■ 12-bits of DATA + 2 SYNC bits for an input PCLK range of 25 MHz to 75 MHz in the 12-bit high frequency
mode. Note: No HS/VS restrictions (raw).
■ 10-bits of DATA + 2 SYNC bits for an input PCLK range of 25 MHz to 100 MHz in the 10-bit mode. Note:
HS/VS restricted to no more than one transition per 10 PCLK cycles.
The DS90UB914A-Q1 chipset has a 2:1 multiplexer which allows customers to select between two Serializer
inputs. The control channel function of the DS90UB913A/DS90UB914A-Q1 chipset provides bidirectional
communication between the image sensor and ECUs. The integrated bidirectional control channel transfers data
bidirectionally over the same differential pair used for video data interface. This interface offers advantages over
other chipsets by eliminating the need for additional wires for programming and control. The bidirectional control
channel bus is controlled via an I2C port. The bidirectional control channel offers asymmetrical communication
and is not dependent on video blanking intervals.
The DS90UB913A/914A chipset offer customers the choice to work with different clocking schemes. The
DS90UB913A/914A chipsets can use an external oscillator as the reference clock source for the PLL (see
section DS90UB913A/914A Operation with External Oscillator as Reference Clock) or PCLK from the imager as
primary reference clock to the PLL (see section DS90UB913A/914A Operation with Pixel Clock from Imager as
Reference Clock.
Transmission Media
The DS90UB913A/914A chipset is intended to be used in a point-to-point configuration through a shielded
twisted pair cable. The Serializer and Deserializer provide internal termination to minimize impedance
discontinuities. The interconnect (cable and connectors) should have a differential impedance of 100Ω, or a
single-ended impedance of 50Ω. The maximum length of cable that can be used is dependent on the quality of
the cable (gauge, impedance), connector, board(discontinuities, power plane), the electrical environment (e.g
power stability, ground noise, input clock jitter, PCLK frequency, etc). The resulting signal quality at the receiving
end of the transmission media may be assessed by monitoring the differential eye opening of the serial data
stream. A differential probe should be used to measure across the termination resistor at the CMLOUTP/N pins.
Figure 21 illustrates the minimum eye width and eye height that is necessary for bit error free operation.
DS90UB913A/914A Operation with External Oscillator as Reference Clock
In some applications, the pixel clock that comes from the imager can have jitter which exceeds the tolerance of
the DS90UB913A/914A chipsets. In this case, the DS90UB913A-Q1 device should be operated by using an
external clock source as the reference clock for the DS90UB913A/914A chipsets. This is the recommended
operating mode. The external oscillator clock output goes through a divide-by-2 circuit in the DS90UB913A-Q1
Serializer and this divided clock output is used as the reference clock for the imager. The output data and pixel
clock from the imager are then fed into the DS90UB913A-Q1 device. Figure 26 shows the operation of the
DS90UB13A/914A chipsets while using an external automotive grade oscillator.
Copyright © 2013, Texas Instruments Incorporated
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