DS90UB914ATRHSTQ1 Datasheet, PDF (18/68 Pages) Texas Instruments – DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit

DS90UB913A-Q1, DS90UB914A-Q1
SNLS443A – MAY 2013 – REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS ^{(1) (2) (3)}
DESERIALIZER SWITCHING CHARACTERISTICS (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
t_DCCJ
Deserializer Cycle- PCLK
to-Cycle Clock Jitter SSCG[3:0] = OFF
(6) (4)
10–bit mode
PCLK = 100 MHz
12–bit low frequency
mode
PCLK = 50 MHz
12–bit high frequency
mode
PCLK = 75 MHz
fdev
Spread Spectrum LVCMOS Output Bus
Clocking Deviation SSC[3:0] = ON
Frequency
(Figure 25),⁽⁴⁾
25 MHz – 100 MHz
fmod
Spread Spectrum
Clocking Modulation
Frequency
25 MHz – 100 MHz
Typ
440
460
565
±0.5 to
±1.5
5 to 50
(6) t_DCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
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Max
1760
Units
730
ps
985
%
kHz
18
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