DS90UB914ATRHSTQ1 Datasheet, PDF (31/68 Pages) Texas Instruments – DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit

DS90UB913A-Q1, DS90UB914A-Q1
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Addr
(Hex)
Name
0x35
PLL Clock
Overwrite
SNLS443A – MAY 2013 – REVISED JUNE 2013
Table 3. DS90UB913A-Q1 Control Registers (continued)
Bits Field
R/W
7:4 RSVD
PIN_LOCK to
3 External
RW
Oscillator
2 RSVD
1
LOCK to External
Oscillator
RW
RW
0 LOCK2OSC
Default
0
0
0
1
Description
Reserved.
Status of mode select pin.
1: Indicates External Oscillator mode is selected by
mode-resistor.
0: External Oscillator mode is not selected by mode-
resistor.
Reserved.
Affects only when 0x03[1]=1 (OV_CLK2PLL) and
0x35[0]=0.
1: Routes GPO3 directly to PLL.
0: Allows PLL to lock to PCLK.
Affects only when 0x03[1]=1 (OV_CLK2PLL).
1: Allows internal OSC clock to feed into PLL.
0: Allows PLL to lock to either PCLK or external clock
from GPO3.
Addr
(Hex)
0x00
0x01
Name
I2C Device ID
Reset
Table 4. DS90UB914A-Q1 Control Registers
Bits
Field
7:1 DEVICE ID
0
Deserializer ID
Select
7:6 RSVD
5 ANAPWDN
4:2 RSVD
1 Digital Reset 1
0 Digital Reset 0
R/W
Default
Description
RW
7-bit address of Deserializer; 0x60'h.
(0110_000x'b) default
0xC0'h
(1100_000) ^{0: De-Serializer Device ID is set using address}
RW
coming from CAD.
1: Register I2C Device ID overrides ID[x].
Reserved.
This register can be set only through local I2C
access.
RW
0
1: Analog power-down : Powers Down the
analog block in the Serializer.
0: No effect.
Reserved.
Digital Reset Resets the entire digital block
RW
0
except registers. This bit is self-clearing.
1: Reset.
0: No effect.
Digital Reset Resets the entire digital block
RW
0
including registers. This bit is self-clearing.
1: Reset.
0: No effect.
Copyright © 2013, Texas Instruments Incorporated
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