DS90UB914ATRHSTQ1 Datasheet, PDF (54/68 Pages) Texas Instruments – DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit

DS90UB913A-Q1, DS90UB914A-Q1
SNLS443A – MAY 2013 – REVISED JUNE 2013
www.ti.com
OSC)
Deserializer GPIO[0:1]
00
01
10
Table 12. BIST Configuration
Oscillator Source
External PCLK
Internal
Internal
BIST Frequency (MHz)
PCLK or External Oscillator
~50
~25
BIST mode provides various options for the PCLK source. Either external pins (GPIO0 and GPIO1) or registers
can be used to program the BIST to use external PCLK or various OSC frequencies. Refer to Table 12 for pin
settings
and
refer
to
Table
4
for
register
settings.
The BIST status can be monitored real-time on the PASS pin. For every frame with error(s), the PASS pin
toggles low for one-half PCLK period. If two consecutive frames have errors, PASS will toggle twice to allow
counting of frames with errors. Once the BIST is done, the PASS pin reflects the pass/fail status of the last BIST
run only for one PCLK cycle. The status can also be read through I2C for the number of frames in errors. BIST
status register retains results until it is reset by a new BIST session or a device reset. To evaluate BIST in
external oscillator mode, both the external oscillator and PCLK need to be present. For all practical purposes, the
BIST status can be monitored from the BIST Error Count register 0x25 on the DS90UB914A Deserializer.
Sample BIST Sequence
Step1. For the DS90UB913A/914A FPD-Link III chipset, BIST Mode is enabled via the BISTEN pin of
DS90UB914A-Q1 FPD-Link III deserializer. The desired clock source is selected through the deserializer GPIO0
and GPIO1 pins as shown in Table 12.
Step2. The DS90UB913A-Q1 Serializer BIST pattern is enabled through the back channel. The BIST pattern is
sent through the FPD-Link III to the deserializer. Once the serializer and deserializer are in the BIST mode and
the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking FPD-Link III
serial stream. If an error in the payload is detected, the PASS pin will switch low for one half of the clock period.
During the BIST test, the PASS output can be monitored and counted to determine the payload error rate.
Step3. To stop the BIST mode, the deserializer BISTEN pin is set LOW. The deserializer stops checking the
data. The final test result is not maintained on the PASS pin. To monitor the BIST status, check the BIST Error
Count register, 0x25 on the Deserializer.
Step4. The link returns to normal operation after the deserializer BISTEN pin is low. Figure 43 shows the
waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple
errors. In most cases, it is difficult to generate errors due to the robustness of the link (differential data
transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect,
or by reducing signal condition enhancements (Rx equalization).
Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 42. AT-Speed BIST System Flow Diagram
54
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