DS90UB914ATRHSTQ1 Datasheet, PDF (25/68 Pages) Texas Instruments – DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit

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DS90UB913A-Q1, DS90UB914A-Q1
SNLS443A – MAY 2013 – REVISED JUNE 2013
0.65
0.60
0.55
0.50
0.45
1E+04
1E+05
1E+06
JITTER FREQUENCY (Hz)
1E+07
Figure 24. Typical Deserializer Input Jitter Tolerance Curve at 1.4Gbps Line Rate
Frequency
F_PCLK+
fdev (max)
fdev F_PCLK
F_PCLK-
1 / fmod
fdev (min)
Time
Figure 25. Spread Spectrum Clock Output Profile
Table 3. DS90UB913A-Q1 Control Registers
Addr
(Hex)
0x00
Name
I2C Device ID
Bits Field
7:1 DEVICE ID
0 SER ID SEL
7 RSVD
6 RDS
5 VDDIO Control
4 VDDIO MODE
0x01 Power and Reset
3 ANAPWDN
2 RSVD
1
DIGITAL
RESET1
0x02
0
DIGITAL
RESET0
R/W
Default Description
7-bit address of Serializer; 0x58'h.
RW
0xB0'h ^{(0101_100x'b) default.}
(1011_000) _{0: Device ID is from ID[x].}
1: Register I2C Device ID overrides ID[x].
Reserved.
Digital Output Drive Strength.
RW
0
1: High Drive Strength.
0: Low Drive Strength.
Auto Voltage Control.
RW
1
1: Enable.
0: Disable.
V_DDIO Voltage set.
RW
1
1: V_DDIO = 3.3V.
0: V_DDIO = 1.8V.
This register can be set only through local I2C access.
RW
0
1: Analog power-down. Powers Down the analog block
in the Serializer.
0: No effect.
RW
0
Reserved.
1: Resets the digital block except for register values.
RW
0
Does not affect device I2C Bus or Device ID. This bit
is self-clearing.
0: Normal Operation.
1: Digital Reset, resets the entire digital block including
RW
1
all register values. This bit is self-clearing.
0: Normal Operation.
Reserved.
Copyright © 2013, Texas Instruments Incorporated
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