DS90UB914ATRHSTQ1 Datasheet, PDF (30/68 Pages) Texas Instruments – DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit

DS90UB913A-Q1, DS90UB914A-Q1
SNLS443A – MAY 2013 – REVISED JUNE 2013
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Addr
(Hex)
Name
0x10
I2C Control
0x11 SCL High Time
0x12 SCL LOW Time
0x13
General Purpose
Control
0x14
BIST Control
0x15–0
x1D
0x1E
BCC Watchdog
Control
0x1F-
0x29
0x2A
0x2B-
0x34
CRC Errors
Table 3. DS90UB913A-Q1 Control Registers (continued)
Bits Field
7 RSVD
6:4 SDA Hold Time
3:0 I2C Filter Depth
7:0 SCL High Time
7:0 SCL Low Time
7:0 GPCR[7:0]
7:3 RSVD
2:1 Clock Source
0 RSVD
7:1
BCC Watchdog
Timer
0
BCC Watchdog
Timer Disable
7:0
BIST Mode CRC
Errors Count
R/W
Default
RW
0x1
RW
0x7
RW
0x82
RW
0x82
RW
0
RW
0x0
Reserved.
RW
0x7F
RW
0
Reserved.
R
0
Reserved.
Description
Reserved.
Internal SDA Hold Time. This field configures the
amount of internal hold time provided for the SDA
input relative to the SCL input. Units are 50ns.
I2C Glitch Filter Depth This field configures the
maximum width of glitch pulses on the SCL and SDA
inputs that will be rejected. Units are 10ns.
I2C Master SCL High Time This field configures the
high pulse width of the SCL output when the Serializer
is the Master on the local I2C bus. Units are 50 ns for
the nominal oscillator clock frequency. The default
value is set to provide a minimum (4µs + 1µs of rise
time for cases where rise time is very fast) SCL high
time with the internal oscillator clock running at 26MHz
rather than the nominal 20MHz.
I2C SCL Low Time This field configures the low pulse
width of the SCL output when the Serializer is the
Master on the local I2C bus. This value is also used as
the SDA setup time by the I2C Slave for providing
data prior to releasing SCL during accesses over the
Bidirectional Control Channel. Units are 50 ns for the
nominal oscillator clock frequency. The default value is
set to provide a minimum (4.7µs + 0.3µs of fall time for
cases where fall time is very fast) SCL low time with
the internal oscillator clock running at 26MHz rather
than the nominal 20MHz.
1: High.
0: Low.
Reserved.
Allows choosing different OSC clock frequencies for
forward channel frame.
OSC Clock Frequency in Functional Mode when OSC
mode is selected or when the selected clock source is
not present e.g. missing PCLK/ External Oscillator.
See Table 5 for oscillator clock frequencies when
PCLK/ External Clock is missing.
Reserved.
The watchdog timer allows termination of a control
channel transaction if it fails to complete within a
programmed amount of time. This field sets the
Bidirectional Control Channel Watchdog Timeout value
in units of 2ms. This field should not be set to 0.
Disable Bidirectional Control Channel Watchdog
Timer.
1: Disables BCC Watchdog Timer operation.
0: Enables BCC Watchdog Timer operation.
Number of CRC Errors in the back channel when in
BIST mode.
30
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