DS90UB914ATRHSTQ1 Datasheet, PDF (15/68 Pages) Texas Instruments – DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit

DS90UB913A-Q1, DS90UB914A-Q1
www.ti.com
SNLS443A – MAY 2013 – REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS ^{(1) (2) (3)}
SERIALIZER SWITCHING CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t_LHT
CML Low-to-High Transition R_L = 100Ω (Figure 8)
Time
150
330
ps
t_HLT
CML High-to-Low Transition R_L = 100Ω (Figure 8)
Time
150
330
ps
t_DIS
Data Input Setup to PCLK Serializer Data Inputs
2
ns
t_DIH
Data Input Hold from PCLK ^{(Figure 14)}
2
ns
t_PLD
Serializer PLL Lock Time
R_L = 100Ω ^{(4) (5)}, (Figure 15)
1
2
ms
t_SD
Serializer Delay ⁽⁵⁾
R_T = 100Ω
10–bit mode
Register 0x03h b[0] (TRFB = 1)
32.5T
38T
44T
ns
(Figure 16)
R_T = 100Ω
12–bit mode
Register 0x03h b[0] (TRFB = 1)
11.75T
13T
15T
ns
(Figure 16)
t_JIND
Serializer Output
Serializer output intrinsic deterministic
Deterministic Jitter
jitter . Measured (cycle-cycle) with
PRBS-7 test pattern
0.13
UI
(3) (6)
t_JINR
Serializer Output Random Serializer output intrinsic random jitter
Jitter
(cycle-cycle). Alternating-1,0 pattern.
0.04
UI
(3) (6)
t_JINT
Peak-to-peak Serializer
Serializer output peak-to-peak jitter
Output Jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measured (cycle-cycle) with
0.396
UI
PRBS-7 test pattern.
(3) (6)
λ_STXBW
δ_STX
Serializer Jitter Transfer
Function -3 dB Bandwidth⁽⁷⁾
Serializer Jitter Transfer
Function (Peaking) ⁽⁷⁾
PCLK = 100 MHz
10–bit mode. Default Registers
PCLK = 75 MHz
12–bit high frequency mode. Default
Registers
PCLK = 50 MHz
12–bit low frequency mode. Default
Registers
PCLK = 100 MHz
10–bit mode. Default Registers
PCLK = 75 MHz
12–bit high frequency mode. Default
Registers
PCLK = 50 MHz
12–bit low frequency mode. Default
Registers
2.2
2.2
2.2
1.06
1.09
1.16
MHz
dB
(1) The Electrical Characteristics tables list verified specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not
verified.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, T_A = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not verified.
(4) t_PLD and t_DDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
(5) Specification is verified by design.
(6) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
(7) Specification is verified by characterization and is not tested in production.
Copyright © 2013, Texas Instruments Incorporated
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