DS90UB914ATRHSTQ1 Datasheet, PDF (39/68 Pages) Texas Instruments – DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit

DS90UB913A-Q1, DS90UB914A-Q1
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SNLS443A – MAY 2013 – REVISED JUNE 2013
Addr
(Hex)
Name
0x24
BIST Control
0x25 Parity Error Count
0x26–0
x3B
0x3C
Oscillator output
divider select
0x3D-
0x3E
0x3F
CML Output
Enable
0x40 SCL High Time
0x41 SCL Low Time
0x42 CRC Force Error
0x43-
0x4C
Table 4. DS90UB914A-Q1 Control Registers (continued)
Bits
Field
7:4 RSVD
3
BIST Pin
Configuration
R/W
Default
RW
1
2:1 BIST Clock Source RW
00
0 BIST Enable
RW
0
7:0 BIST Error Count
7:2 RSVD
R
0
Reserved.
1:0
OSC OUT
DIVIDER SEL
RW
0
7:5 RSVD
4 CML OUT Enable
3:0 RSVD
Reserved.
RW
1
7:0 SCL High Time
RW
0x82
7:0 SCL Low Time
RW
0x82
7:2 RSVD
1
Force Back
Channel Error
Force One Back
0 Channel Error
RW
0
RW
0
Reserved.
Description
Reserved.
Bist Configured through Pin.
1: Bist configured through pin.
0: Bist configured through register bit
"reg_24[0]".
BIST Clock Source.
See Table 6
BIST Control.
1: Enabled.
0: Disabled.
Number of Forward channel Parity errors in the
BIST mode.
Reserved.
Selects the divider for the OSC clock out on
PCLK when system is not locked and selected
by OEN/OSS_SEL 0x02[5]:
00: 50M (+/- 30%)
01: 25M (+/- 30%)
1X: 12.5M (+/- 30%)
Reserved.
0: CML Loop-through Driver is powered up.
1: CML Loop-through Driver is powered down.
Reserved.
I2C Master SCL High Time This field configures
the high pulse width of the SCL output when
the De-Serializer is the Master on the local I2C
bus. Units are 50 ns for the nominal oscillator
clock frequency. The default value is set to
provide a minimum (4μs + 0.3μs of rise time for
cases where rise time is very fast) SCL high
time with the internal oscillator clock running at
26MHz rather than the nominal 20MHz.
I2C SCL Low Time This field configures the low
pulse width of the SCL output when the De-
Serializer is the Master on the local I2C bus.
This value is also used as the SDA setup time
by the I2C Slave for providing data prior to
releasing SCL during accesses over the
Bidirectional Control Channel. Units are 50 ns
for the nominal oscillator clock frequency. The
default value is set to provide a minimum
(4.7µs + 0.3µs of fall time for cases where fall
time is very fast) SCL low time with the internal
oscillator clock running at 26MHz rather than
the nominal 20MHz.
Reserved.
1: This bit introduces multiple errors into Back
channel frame.
0: No effect.
1: This bit introduces ONLY one error into Back
channel frame. Self clearing bit.
0: No effect.
Copyright © 2013, Texas Instruments Incorporated
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