DS90UB914ATRHSTQ1 Datasheet, PDF (4/68 Pages) Texas Instruments – DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit

DS90UB913A-Q1, DS90UB914A-Q1
SNLS443A – MAY 2013 – REVISED JUNE 2013
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Table 1. Pin Descriptions (continued)
Pin Name
Pin No.
I/O, Type
Description
GPO[3]/CLKIN
18
Input/Output, GPO3 can be configured to be the output for input signals coming from the GPIO3
LVCMOS
pin on the Deserializer or can be configured to be the output of the local register
setting on the Serializer. It can also be configured to be the input clock pin when
the DS90UB913A-Q1 Serializer is working with an external oscillator. See
Applications Information section for a detailed description of the
DS90UB913A/914A chipsets working with an external oscillator.
BIDIRECTIONAL CONTROL BUS - I2C-COMPATIBLE
SCL
SDA
MODE
4
Input/Output, Clock line for the bidirectional control bus communication.
Open Drain SCL requires an external pull-up resistor to V_DDIO.
5
Input/Output, Data line for the bidirectional control bus communication.
Open Drain SDA requires an external pull-up resistor to V_DDIO.
Device mode select.
8
Input, LVCMOS Resistor to Ground and 10 kΩ pull-up to 1.8V rail. MODE pin on the Serializer can
w/ pull down be used to select whether the system is running off the PCLK from the imager or
an external oscillator. See details in Table 7.
ID[x]
Device ID Address Select.
6
Input, analog The ID[x] pin on the Serializer is used to assign the I2C device address. Resistor
to Ground and 10 kΩ pull-up to 1.8V rail. See Table 9.
CONTROL AND CONFIGURATION
PDB
Power down Mode Input Pin.
9
Input, LVCMOS
w/ pull down
PDB = H, Serializer is enabled and is ON.
PDB = L, Serializer is in Power Down mode. When the Serializer is in Power
Down, the PLL is shutdown, and IDD is minimized. Programmed control register
data are NOT retained and reset to default values.
RES
7
Input, LVCMOS Reserved.
w/ pull down This pin MUST be tied LOW.
FPD–Link III INTERFACE
DOUT+
13
Input/Output, Non-inverting differential output, bidirectional control channel input. The
CML
interconnect must be AC Coupled with a 0.1µF capacitor.
DOUT-
12
Input/Output, Inverting differential output, bidirectional control channel input. The interconnect
CML
must be AC Coupled with a 0.1µF capacitor. For applications using single-ended
coaxial interconnect, terminate to Ground with a 0.047µF capacitor.
POWER AND GROUND
VDDPLL
10
Power, Analog PLL Power, 1.8V ±5%.
VDDT
11
Power, Analog Tx Analog Power, 1.8V ±5%.
VDDCML
14
Power, Analog CML & Bidirectional Channel Driver Power, 1.8V ±5%.
VDDD
28
Power, Digital Digital Power, 1.8V ±5%.
VDDIO
VSS
25
DAP
Power, Digital
Ground, DAP
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from
V_DDIO. V_DDIO can be connected to a 1.8V ±5% or 2.8±10% or 3.3V ±10%.
DAP must be grounded. DAP is the large metal contact at the bottom side, located
at the center of the WQFN package. Connected to the ground plane (GND) with at
least 9 vias.
4
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