DS90UB914ATRHSTQ1 Datasheet, PDF (53/68 Pages) Texas Instruments – DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit

DS90UB913A-Q1, DS90UB914A-Q1
www.ti.com
SNLS443A – MAY 2013 – REVISED JUNE 2013
EMI Reduction
Deserializer Staggered Output
The receiver staggers output switching to provide a random distribution of transitions within a defined window.
Outputs transitions are distributed randomly. This minimizes the number of outputs switching simultaneously and
helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall EMI.
Spread Spectrum Clock Generation(SSCG) on the Deserializer
The DS90UB914A-Q1 parallel data and clock outputs have programmable SSCG ranges from 25 MHz to 100
MHz. The modulation rate and modulation frequency variation of output spread is controlled through the SSCG
control registers on the DS90UB914A-Q1 device. SSCG profiles can be generated using bits [3:0] in register
0x02 in the Deserializer.
Powerdown
The SER has a PDB input pin to ENABLE or powerdown the device. Enabling PDB on the SER will disable the
link to save power. If PDB=HIGH, the SER will operate at its internal default oscillator frequency when the input
PCLK stops. When the PCLK starts again, the SER will then lock to the valid input PCLK and transmit the data to
the DES. When PDB=LOW, the high-speed driver outputs are static HIGH.
The DES has a PDB input pin to ENABLE or Powerdown the device. Enabling PDB on the DES will disable the
link to save power. If PDB=HIGH, the DES will lock to the input stream and assert the LOCK pin (HIGH) and
output valid data. When PDB=LOW, all outputs are in TRI-STATE.
Pixel Clock Edge Select (TRFB / RRFB)
The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge
that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register
is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the
data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0,
data is strobed on the falling edge of the PCLK.
PCLK
DIN/
ROUT
TRFB/RRFB: 0
TRFB/RRFB: 1
Figure 41. Programmable PCLK Strobe Select
Power Up Requirements and PDB Pin
It is required to delay and release the PDB Signal after VDD (VDDn and VDDIO) power supplies have settled to
the recommended operating voltage. An external RC network can be connected to the PDB pin to ensure PDB
arrives after all the VDD has stabilized.
Built In Self Test
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and low-
speed back channel. This is useful in the prototype stage, equipment production, and in-system test and also for
system diagnostics.
BIST Configuration and Status
The chipset can be programmed into BIST mode using either pins or registers on the DES only. By default BIST
configuration is controlled through pins. BIST can be configured via registers using BIST Control register (0x24).
Pin-based configuration is defined as follows:
• BISTEN = HIGH: Enable the BIST mode, BISTEN = LOW: Disable the BIST mode.
• Deserializer GPIO0 and GPIO1: Defines the BIST clock source (PCLK vs. various frequencies of internal
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