DS90UB914ATRHSTQ1 Datasheet, PDF (32/68 Pages) Texas Instruments – DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit

DS90UB913A-Q1, DS90UB914A-Q1
SNLS443A – MAY 2013 – REVISED JUNE 2013
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Addr
(Hex)
0x02
0x03
Name
General
Configuration 0
General
Configuration 1
Table 4. DS90UB914A-Q1 Control Registers (continued)
Bits
Field
R/W
7 RSVD
6 RSVD
5 Auto-Clock
RW
4 SSCG LFMODE
RW
3:0 SSCG
RW
7
RX Parity Checker
Enable
RW
6
TX CRC Checker
Enable
RW
5 V_DDIO Control
RW
4 V_DDIO Mode
RW
I2C Pass-Through
3
RW
2 AUTO ACK
RW
1 Parity Error Reset
RW
0 RRFB
RW
Default
0
0
0
1
1
1
0
1
0
0
1
Description
Reserved.
Reserved.
1: Output PCLK or OSC clock when not
LOCKED.
0: Only PCLK.
1: Selects 8x mode for 10-18 MHz frequency
range in SSCG.
0: SSCG running at 4X mode.
SSCG Select.
0000: Normal Operation, SSCG OFF.
0001: fmod (kHz) PCLK/2168, fdev +/-0.50%.
0010: fmod (kHz) PCLK/2168, fdev +/-1.00%.
0011: fmod (kHz) PCLK/2168, fdev +/-1.50%.
0100: fmod (kHz) PCLK/2168, fdev +/-2.00%.
0101: fmod (kHz) PCLK/1300, fdev +/-0.50%.
0110: fmod (kHz) PCLK/1300, fdev +/-1.00%.
0111: fmod (kHz) PCLK/1300, fdev +/-1.50%.
1000: fmod (kHz) PCLK/1300, fdev +/-2.00%.
1001: fmod (kHz) PCLK/868, fdev +/-0.50%.
1010: fmod (kHz) PCLK/868, fdev +/-1.00%.
1011: fmod (kHz) PCLK/868, fdev +/-1.50%.
1100: fmod (kHz) PCLK/868, fdev +/-2.00%.
1101: fmod (kHz) PCLK/650, fdev +/-0.50%.
1110: fmod (kHz) PCLK/650, fdev +/-1.00%.
1111: fmod (kHz) PCLK/650, fdev +/-1.50%.
Note: This register should be changed only
after disabling SSCG.
Forward Channel Parity Checker Enable.
1: Enable.
0: Disable.
Back Channel CRC Generator Enable.
1: Enable.
0: Disable.
Auto voltage control.
1: Enable (auto detect mode).
0: Disable.
VDDIO voltage set.
1: 3.3V
0: 1.8V
II2C Pass-Through Mode.
1: Pass-Through Enabled. SER Alias 0x07 and
Slave Alias 0x09- 0x17.
0: Pass-Through Disabled.
Automatically Acknowledge I2C Remote Write
When enabled, I2C writes to the Deserializer
(or any remote I2C Slave, if I2C PASS ALL is
enabled) are immediately acknowledged
without waiting for the Deserializer to
acknowledge the write. The accesses are then
remapped to address specified in 0x06. This
allows I2C bus without LOCK.
1: Enable.
0: Disable.
Parity Error Reset, This bit is self-clearing.
1: Parity Error Reset.
0: No effect.
Pixel Clock Edge Select.
1: Parallel Interface Data is strobed on the
Rising Clock Edge.
0: Parallel Interface Data is strobed on the
Falling Clock Edge.
32
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