DS90UB914ATRHSTQ1 Datasheet, PDF (6/68 Pages) Texas Instruments – DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit

DS90UB913A-Q1, DS90UB914A-Q1
SNLS443A – MAY 2013 – REVISED JUNE 2013
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Table 2. Pin Descriptions (continued)
Pin Name
Pin No.
I/O, Type
Description
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
SCL
SDA
MODE
2
Input/Output, Clock line for the bidirectional control bus communication.
Open Drain SCL requires an external pull-up resistor to V_DDIO.
1
Input/Output, Data line for bidirectional control bus communication
Open Drain SDA requires an external pull-up resistor to V_DDIO.
Device mode select pin
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. The MODE pin on the Deserializer
can be used to configure the Serializer and Deserializer to work in different input
PCLK range. See details in Table 8.
12– bit low frequency mode – (25- 50 MHz operation):
In this mode, the Serializer and Deserializer can accept up to 12-bits DATA+2 SYNC.
37
Input, LVCMOS
w/ pull up
Input PCLK range is from 25MHz to 50MHz. Note: No HS/VS restrictions.
12– bit high frequency mode – (25-75 MHz operation): In this mode, the Serializer
and Deserializer can accept up to 12-bits DATA + 2 SYNC. Input PCLK range is from
25MHz to 75MHz. Note: No HS/VS restrictions.
10–bit mode– (25–100 MHz operation):
In this mode, the Serializer and Deserializer can accept up to 10-bits DATA + 2
SYNC. Input PCLK frequency can range from 25 MHz to 100MHz. Note: HS/VS
restricted to no more than one transition per 10 PCLK cycles.
Please refer to Table 8 on how to configure the MODE pin on the Deserializer.
IDx[0:1]
35,34
Input, analog
The IDx[0] and IDx[1] pins on the Deserializer are used to assign the I2C device
address. Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 10
Input pin to select the Slave Device Address.
Input is connected to external resistor divider to set programmable Device ID address.
CONTROL AND CONFIGURATION
PDB
Power down Mode Input Pin.
30
Input, LVCMOS
w/ pull down
PDB = H, Deserializer is enabled and is ON.
PDB = L, Deserializer is in power down mode. When the Deserializer is in power
down mode, programmed control register data are NOT retained and reset to default
values.
LOCK
LOCK Status Output Pin.
48
Output,
LVCMOS
LOCK = H, PLL is Locked, outputs are active.
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL control register. May be used as Link Status.
BISTEN
Input
BIST Enable pin
6
LVCMOS w/ BISTEN=H, BIST Mode is enabled.
pulldown BISTEN=L, BIST Mode is disabled.
PASS
PASS Output Pin for BIST mode.
47
Output,
LVCMOS
PASS = H, ERROR FREE Transmission.
PASS = L, one or more errors were detected in the received payload.
See BIST section for more information. Leave Open if unused. Route to test point
(pad) recommended.
OEN
Input
Output Enable Input.
5
LVCMOS w/ Refer to Table 11.
pulldown
OSS_SEL
Input
Output Sleep State Select Pin
4
LVCMOS w/ Refer to Table 11.
pulldown
SEL
46
Input
LVCMOS w/
pulldown
MUX Select line.
SEL = L, RIN0+/- input. This selects input A as the active channel on the Deserializer.
SEL = H, RIN1+/- input. This selects input B as the active channel on the
Deserializer.
FPD–Link III INTERFACE
RIN0+
41
Input/Output, Non-Inverting Differential input, bidirectional control channel. The IO must be AC
CML
coupled with a 0.1µF capacitor.
RIN0-
42
Input/Output,
CML
Inverting Differential input, bidirectional control channel. The IO must be AC coupled
with a 0.1µF capacitor. For applications using single-ended coaxial interconnect,
terminate to Ground with a 0.047µF capacitor.
RIN1+
32
Input/Output, Non-Inverting Differential input, bidirectional control channel. The IO must be AC
CML
coupled with a 0.1µF capacitor.
6
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