DS90UB914ATRHSTQ1 Datasheet, PDF (38/68 Pages) Texas Instruments – DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit

DS90UB913A-Q1, DS90UB914A-Q1
SNLS443A – MAY 2013 – REVISED JUNE 2013
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Addr
(Hex)
0x21
0x22
0x23
Name
I2C Control 1
I2C Control 2
General Purpose
Control
Table 4. DS90UB914A-Q1 Control Registers (continued)
Bits
Field
R/W
7
I2C Pass-Through
All
RW
6:4 I2C SDA Hold
RW
3:0 I2C Filter Depth
RW
7
Forward Channel
Sequence Error
R
6
Clear Sequence
Error
RW
5 RSVD
4:3 SDA Output Delay RW
2 Local Write Disable RW
1
I2C Bus Timer
Speedup
RW
0
I2C Bus Timer
Disable
RW
7:0 GPCR
RW
Default
0
0
0
0
0
0
0
0
0
0
Description
1: Enable Forward Control Channel pass-
through of all I2C accesses to I2C IDs that do
not match the Deserializer I2C ID. The I2C
accesses are then remapped to address
specified in register 0x06 (SER ID).
0: Enable Forward Control Channel pass-
through only of I2C accesses to I2C IDs
matching either the remote Serializer ID or the
remote I2C IDs.
Internal SDA Hold Time This field configures
the amount of internal hold time provided for
the SDA input relative to the SCL input. Units
are 50ns.
I2C Glitch Filter Depth This field configures the
maximum width of glitch pulses on the SCL and
SDA inputs that will be rejected. Units are 10ns.
Control Channel Sequence Error Detected This
bit indicates a sequence error has been
detected in forward control channel.
1: If this bit is set, an error may have occurred
in the control channel operation.
0: No forward channel errors have been
detected on the control channel.
Clears the Sequence Error Detect bit.
Reserved.
SDA Output Delay This field configures output
delay on the SDA output. Setting this value will
increase output delay in units of 50ns. Nominal
output delay values for SCL to SDA are:
00 : ~350ns
01: ~400ns
10: ~450ns
11: ~500ns
Disable Remote Writes to local registers
Setting this bit to a 1 will prevent remote writes
to local device registers from across the control
channel. This prevents writes to the
Deserializer registers from an I2C master
attached to the Serializer. Setting this bit does
not affect remote access to I2C slaves at the
Deserializer.
Speed up I2C Bus Watchdog Timer.
1: Watchdog Timer expires after approximately
50µs.
0: Watchdog Timer expires after approximately
1s.
Disable I2C Bus Watchdog Timer When the
I2C Watchdog Timer may be used to detect
when the I2C bus is free or hung up following
an invalid termination of a transaction. If SDA is
high and no signaling occurs for approximately
1 second, the I2C bus will assumed to be free.
If SDA is low and no signaling occurs, the
device will attempt to clear the bus by driving 9
clocks on SCL.
Scratch Register.
38
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