DS90UB914ATRHSTQ1 Datasheet, PDF (26/68 Pages) Texas Instruments – DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit

DS90UB913A-Q1, DS90UB914A-Q1
SNLS443A – MAY 2013 – REVISED JUNE 2013
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Addr
(Hex)
0x03
0x04
0x05
Name
General
Configuration
Mode Select
Table 3. DS90UB913A-Q1 Control Registers (continued)
Bits Field
R/W
Default Description
7
RX CRC Checker
Enable
RW
Back-channel CRC Checker Enable.
1
1:Enable.
0: Disable.
6
TX Parity
Generator Enable
RW
Forward channel Parity Generator Enable.
1
1: Enable.
0: Disable.
5 CRC Error Reset RW
Clear CRC Error Counters.
0
This bit is NOT self-clearing.
1: Clear Counters.
0: Normal Operation.
I2C Remote Write
4 Auto
RW
Acknowledge
Automatically Acknowledge I2C Remote Write.
The mode works when the system is LOCKed.
1: Enable: When enabled, I2C writes to the
Deserializer (or any remote I2C Slave, if I2C PASS
0
ALL is enabled) are immediately acknowledged
without waiting for the Deserializer to acknowledge the
write. The accesses are then remapped to address
specified in 0x06.
0: Disable.
1: Enable Forward Control Channel pass-through of all
I2C accesses to I2C IDs that do not match the
3
I2C Pass-
Through All
RW
Serializer I2C ID. The I2C accesses are then
0
remapped to address specified in register 0x06.
0: Enable Forward Control Channel pass-through only
of I2C accesses to I2C IDs matching either the
remote Deserializer ID or the remote I2C IDs.
2
I2C Pass-
Through
I2C Pass-Through Mode.
RW
1
1: Pass-Through Enabled. DES Alias 0x07 and Slave
Alias 0x09.
0: Pass-Through Disabled.
1 OV_CLK2PLL
RW
1:Enabled : When enabled this register overrides the
clock to PLL mode (External Oscillator mode or Direct
PCLK mode) defined through MODE pin and allows
0
selection through register 0x35 in the Serializer.
0: Disabled : When disabled, Clock to PLL mode
(External Oscillator mode or Direct PCLK mode) is
defined through MODE pin on the Serializer.
0 TRFB
Pixel Clock Edge Select.
1: Parallel Interface Data is strobed on the Rising
RW
1
Clock Edge.
0: Parallel Interface Data is strobed on the Falling
Clock Edge.
Reserved.
7 RSVD
RW
0
Reserved.
6 RSVD
RW
0
Reserved.
5
MODE_OVERRI
DE
RW
Allows overriding mode select bits coming from back-
0
channel.
1: Overrides MODE select bits.
0: Does not override MODE select bits.
4
MODE_UP_TO_
DATE
R
0
Indicates that the status of mode select from
Deserializer is up to date.
3
Pin_MODE_12–bi
t High Frequency
R
0
1: 12-bit high frequency mode is selected.
0: 12-bit high frequency mode is not selected.
2
Pin_MODE_10–bi
t mode
R
0
1: 10-bit mode is selected.
0: 10-bit mode is not selected.
1:0 RSVD
Reserved.
26
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