DS90UB914ATRHSTQ1 Datasheet, PDF (20/68 Pages) Texas Instruments – DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit

DS90UB913A-Q1, DS90UB914A-Q1
SNLS443A – MAY 2013 – REVISED JUNE 2013
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BIDIRECTIONAL CONTROL BUS DC TIMING SPECIFICATIONS (SCL, SDA) - I2C COMPLIANT⁽¹⁾
Over recommended supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Recommended Input Timing Requirements
V_IH
V_IL
V_HY
V_OL
I_IN
t_R
t_F
t_SU;DAT
t_HD;DAT
t_SP
C_IN
Input High Level
Input Low Level
Input Hysteresis
Output Low Level
Input Current
SDA Rise Time-READ
SDA Fall Time-READ
SDA and SCL
SDA and SCL
SDA, I_OL=0.5mA
SDA or SCL, V_IN=V_DDIO OR GND
SDA, RPU = 10kΩ, Cb ≤ 400pF
(Figure 6)
(See Figure 6)
(See Figure 6)
SDA or SCL
0.7*V_DDIO
GND
0
—10
V_DDIO
V
0.3*V_DDIO
V
>50
mV
0.4
V
10
µA
430
ns
20
ns
560
ns
615
ns
50
ns
<5
pF
(1) Specification is verified by design.
SDA
t_f
SCL
START
t_LOW
t_r
t_f
t_HD;STA
t_BUF
t_r
t_HD;STA
t_HD;DAT
t_HIGH
t_SU;DAT
t_SU;STA
t_SU;STO
REPEATED
START
Figure 6. Bi-directional Control Bus Timing
STOP START
AC Timing Diagrams and Test Circuits
Device Pin Name
PCLK
(RFB = H)
Signal Pattern
T
D_IN/R_OUT
Figure 7. “Worst Case” Test Pattern
Vdiff
80%
20%
80%
Vdiff = 0V
20%
t_LHT
t_HLT
Vdiff = (D_OUT+) - (D_OUT-)
Figure 8. Serializer CML Output Load and Transition Times
20
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