DS90UB913Q_13 Datasheet, PDF (9/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
www.ti.com
SNLS420B – JULY 2012 – REVISED APRIL 2013
Electrical Characteristics^(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
V_OL
Low Level Output
Voltage
V_DDIO = 1.71V to 1.89V Deserializer
I_OL = +4 mA
LVCMOS Outputs
GND
I_OS
Output Short Circuit
V_OUT = 0V
Serializer
Current
GPO Outputs
-11
Deserializer
LVCMOS Outputs
-17
I_OZ
TRI-STATE® Output
Current
PDB = 0V,
V_OUT = 0V or V_DD
LVCMOS Outputs
-20
LVCMOS DC SPECIFICATIONS 2.8V I/O (SER INPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)
V_IH
High Level Input
V_IN = 2.52V to 3.08V
Voltage
0.7 V_IN
V_IL
Low Level Input
V_IN = 2.52V to 3.08V
Voltage
GND
I_IN
Input Current
V_IN = 0V or 3.08V
V_IN = 2.52V to 3.08V
-20
±1
V_OH
High Level Output
V_DDIO = 2.52V to 3.08V
Voltage
I_OH = −4 mA
V_DDIO - 0.4
V_OL
Low Level Output
Voltage
V_DDIO =2.52V to 3.08V Deserializer
I_OL = +4 mA
LVCMOS Outputs
GND
I_OS
Output Short Circuit
V_OUT = 0V
Serializer
Current
GPO Outputs
-11
Deserializer
LVCMOS Outputs
-20
I_OZ
TRI-STATE® Output PDB = 0V,
Current
V_OUT = 0V or V_DD
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
LVCMOS Outputs
-20
|V_OD|
Output Differential
Voltage
R_L = 100Ω (Figure 8)
268
340
ΔV_OD
Output Differential
Voltage Unbalance
R_L = 100Ω
1
V_OS
ΔV_OS
Output Differential
Offset Voltage
Offset Voltage
Unbalance
R_L = 100Ω (Figure 8)
R_L = 100Ω
V_DD -
V_OD/2
1
I_OS
Output Short Circuit DOUT+/- = 0V
Current
-26
R_T
Differential Internal
Differential across DOUT+ and DOUT-
Termination Resistance
80
100
CML RECEIVER DC SPECIFICATIONS (RIN0+,RIN0–,RIN1+,RIN1– )
I_IN
Input Current
V_IN = V_DD or 0V,
V_DD = 1.89V
-20
1
R_T
Differential Internal
Differential across RIN+ and RIN-
Termination Resistance
80
100
CML RECEIVER AC SPECIFICATIONS (RIN0+,RIN0–,RIN1+,RIN1– )
Minimum allowable
Line Rate = 1.4Gbps (Figure 10)
|V_swing|
swing for 1010
135
pattern ⁽⁴⁾
CMLMONITOR OUTPUT DRIVER SPECIFICATIONS(CMLOUTP, CMLOUTN)
E_w
Differntial Output Eye R_L = 100Ω
Opening
Jitter Frequency>f/40 (Figure 19)
0.45
E_H
Differential Output Eye
Height
200
SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD
Max
0.45
+20
V_IN
0.3 V_IN
+20
V_DDIO
0.4
+20
412
50
50
120
+20
120
Units
V
mA
µA
V
µA
V
V
mA
µA
mV
mV
V
mV
mA
Ω
µA
Ω
mV
UI
mV
(4) Specification is ensured by characterization and is not tested in production.
Copyright © 2012–2013, Texas Instruments Incorporated
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