DS90UB913Q_13 Datasheet, PDF (40/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
SNLS420B – JULY 2012 – REVISED APRIL 2013
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MODE Pin on Deserializer
The mode pin on the Deserializer can be used to configure the device to work in the 12-bit low frequency mode,
12- bit high frequency mode or the 10 bit mode of operation. Internally, the DS90UB913/914Q chipset operates
in a divide-by-1 mode in the 12- bit low frequency mode, divide-by-2 mode in the 10-bit mode and a divide-by-1.5
mode in the 12- bit high frequency mode. The pin must be pulled to V_DD (1.8V, not V_DDIO) with a 10 kΩ resistor
and a pull down resistor (R_MODE) of the recommended value to set the different modes in the Deserializer as
mentioned in Table 6. The Deserializer automatically configures the Serializer to correct mode via the back-
channel. The recommended maximum resistor tolerance is 1%
.
1.8V
HOST
SCL
SDA
V_DDIO
RPU
RPU
10k
MODE
R_MODE
DS90UB914Q
SCL
SDA
To Other
Devices
Figure 27. Mode Pin Configuration on DS90UB914Q Deserializer
Table 6. DS90UB914Q Deserializer MODE Resistor Value
DS90UB914Q Deserializer MODE resistor Value
MODE Select
12-bit low frequency mode 10-50 MHz PCLK, 10/12 bits DATA+ 2 SYNC
12-bit high frequency mode 15-75 MHz PCLK, 10/12 bits DATA+ 2 SYNC
10-bit mode 20 MHz – 100 MHz PCLK, 10 bits DATA+ 2 SYNC
R_MODE Resistor Value
0kΩ
3kΩ
11kΩ
Line Rate Calculations for the DS90UB913/914Q
The DS90UB913Q device divides the clock internally by divide-by-1 in the 12 bit low frequency mode, by divide-
by-2 in the 10-bit mode and by divide-by-1.5 in the 12-bit high frequency mode. Conversely, the DS90UB914Q
multiplies the recovered serial clock to generate the proper pixel clock output frequency. Thus the maximum line
rate in the three different modes remains 1.4Gbps. The following are the formulae used to calculate the
maximum line rate in the different modes.
• For 12 bit low frequency mode, Line rate = f_PCLK*28; e.g. f_PCLK=50MHz, line rate = 50*28=1.4Gbps
• For 10 bit mode, Line rate = f_PCLK/2*28; e.g. f_PCLK=100MHz, line rate = (100/2)*28=1.4Gbps
• For the 12 bit high frequency mode, Line rate = f_PCLK*(2/3)*28; e.g. f_PCLK=75MHz, line rate =
(75)*(2/3)*28=1.4Gbps
Deserializer Multiplexer Input
The DS90UB914Q offers a 2:1 multiplexer that can be used to select which camera is used as the input.
Figure 28 shows the operation of the 2:1 multiplexer in the Deserializer. The selection of the camera can be pin
controlled as well as register controlled. Both the Deserializer inputs cannot be enabled at the same time. If the
Serializer A is selected as the active Serializer, the back-channel for Deserializer A turns ON and vice versa. To
switch between the two cameras, first the Serializer B has to be selected using the SEL pin/register on the
Deserializer. After that the back channel driver for Deserializer B has to be enabled using the register in the
Deserializer.
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