DS90UB913Q_13 Datasheet, PDF (26/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
SNLS420B – JULY 2012 – REVISED APRIL 2013
www.ti.com
Table 1. DS90UB913Q Control Registers (continued)
Addr
(Hex)
Name
Bits Field
R/W
7:5 RSVD
4:3 SDA Output Delay RW
2 Local Write Disable RW
0x0F I²C Master Config
1
I2C Bus Timer
Speed up
RW
0
I2C Bus Timer
Disable
RW
7 RSVD
6:4 SDA Hold Time
RW
0x10
I2C Control
3:0 I2C Filter Depth
RW
0x11 SCL High Time 7:0 SCL High Time
RW
0x12 SCL LOW Time 7:0 SCL Low Time
RW
0x13
General Purpose
Control
7:0 GPCR[7:0]
RW
Default Description
00
0
0
0
0x1
0x7
0x82
0x82
0
Reserved
SDA Output Delay This field configures output delay on
the SDA output. Setting this value will increase output
delay in units of 50ns. Nominal output delay values for
SCL to SDA are:
00 : 350ns
01: 400ns
10: 450ns
11: 500ns
Disable Remote Writes to Local Registers Setting this bit
to a 1 will prevent remote writes to local device registers
from across the control channel. This prevents writes to
the Serializer registers from an I²C master attached to
the Deserializer. Setting this bit does not affect remote
access to I²C slaves at the Serializer.
Speed up I2C Bus Watchdog Timer
1: Watchdog Timer expires after approximately 50
microseconds
0: Watchdog Timer expires after approximately 1 second.
1. Disable I²C Bus Watchdog Timer When the I²C
Watchdog Timer may be used to detect when the I²C bus
is free or hung up following an invalid termination of a
transaction. If SDA is high and no signalling occurs for
approximately 1 second, the I²C bus will assumed to be
free. If SDA is low and no signaling occurs, the device
will attempt to clear the bus by driving 9 clocks on SCL
0: No effect
Reserved
Internal SDA Hold Time. This field configures the amount
of internal hold time provided for the SDA input relative to
the SCL input. Units are 50ns.
I2C Glitch Filter Depth This field configures the maximum
width of glitch pulses on the SCL and SDA inputs that will
be rejected. Units are 10ns.
I2C Master SCL High Time This field configures the high
pulse width of the SCL output when the Serializer is the
Master on the local I2C bus. Units are 50 ns for the
nominal oscillator clock frequency. The default value is
set to provide a minimum (4µs + 1µs of rise time for
cases where rise time is very fast) SCL high time with the
internal oscillator clock running at 26MHz rather than the
nominal 20MHz.
I²C SCL Low Time This field configures the low pulse
width of the SCL output when the Serializer is the Master
on the local I²C bus. This value is also used as the SDA
setup time by the I²C Slave for providing data prior to
releasing SCL during accesses over the Bidirectional
Control Channel. Units are 50 ns for the nominal
oscillator clock frequency. The default value is set to
provide a minimum (4.7µs + 0.3µs of fall time for cases
where fall time is very fast) SCL low time with the internal
oscillator clock running at 26MHz rather than the nominal
20MHz.
1: High
0: Low
26
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