DS90UB913Q_13 Datasheet, PDF (23/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
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Addr
(Hex)
Name
0x03
General
Configuration
0x04
0x05
Mode Select
SNLS420B – JULY 2012 – REVISED APRIL 2013
Table 1. DS90UB913Q Control Registers (continued)
Bits Field
7
RX CRC Checker
Enable
6
TX Parity
Generator Enable
5 CRC Error Reset
4
I²C Remote Write
Auto Acknowledge
3 I²C Pass All
2
I²C
PASSTHROUGH
1 OV_CLK2PLL
0 TRFB
7 RSVD
6 RSVD
5
MODE_OVERRID
E
4
MODE_UP To
DATE
3
Pin_MODE_12–bit
High Frequency
2
Pin_MODE_10–bit
mode
1:0 RSVD
R/W Default Description
Back-channel CRC Checker Enable
RW
1
1:Enabled
0:Disabled
Forward channel Parity Generator Enable
RW
1
1: Enable
0: Disable
Clear CRC Error Counters.
RW
0
This bit is NOT self-clearing.
1: Clear Counters
0: Normal Operation
Automatically Acknowledge I2C Remote Write
The mode works when the system is LOCKed.
1: Enable: When enabled, I²C writes to the Deserializer
RW
0
(or any remote I2C Slave, if I²C PASS ALL is enabled)
are immediately acknowledged without waiting for the
Deserializer to acknowledge the write. The accesses are
then remapped to address specified in 0x06.
0: Disable
1: Enable Forward Control Channel pass-through of all
I²C accesses to I2C Slave IDs that do not match the
Serializer I2C Slave ID. The I²C accesses are then
RW
0
remapped to address specified in register 0x06.
0: Enable Forward Control Channel pass-through only of
I²C accesses to I²C Slave IDs matching either the remote
Deserializer Slave ID or the remote Slave ID.
I²C Pass-Through Mode
RW
1
0: Pass-Through Disabled
1: Pass-Through Enabled
1:Enabled : When enabled this registers overrides the
clock to PLL mode (External Oscillator mode or Direct
PCLK mode) defined through MODE pin and allows
RW
0
selection through register 0x35 in the Serializer
0: Disabled : When disabled,cClock to PLL mode
(External Oscillator mode or Direct PCLK mode) is
defined through MODE pin on the Serializer.
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising Clock
RW
1
Edge.
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
RESERVED
RW
0
Reserved
RW
0
Reserved.
Allows overriding mode select bits coming from back-
RW
0
channel
1: Overrides MODE select bits
0: Does not override MODE select bits
R
0
Indicates that the status of mode select from Deserializer
is up to date
R
0
1: 12 bit high frequency mode is selected.
0: 12 bit high frequency mode is not selected.
R
0
1: 10 bit mode is selected.
0: 10 bit mode is not selected.
Reserved
Copyright © 2012–2013, Texas Instruments Incorporated
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