DS90UB913Q_13 Datasheet, PDF (15/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
www.ti.com
SNLS420B – JULY 2012 – REVISED APRIL 2013
Deserializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
t_DCCJ
Deserializer Cycle- PCLK
to-Cycle Clock Jitter SSCG[3:0] = OFF⁽³⁾⁽¹⁾
10–bit mode
PCLK=100MHz
12–bit low frequency
mode
PCLK=50MHz
12–bit high frequency
mode
PCLK=75MHz
fdev
Spread Spectrum LVCMOS Output Bus
10 MHz–100 MHz
Clocking Deviation SSC[3:0] = ON (Figure 23)⁽¹⁾
Frequency
fmod
Spread Spectrum
Clocking Modulation
Frequency
10 MHz–100 MHz
Typ
440
460
565
±0.5 to
±1.5
5 to 50
(3) t_DCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
Max
1760
730
985
Units
ps
%
kHz
AC Timing Specifications (SCL, SDA) - I²C Compliant
Over recommended supply and temperature ranges unless otherwise specified.(Figure 4)
Symbol
Parameter
Conditions
Min
Recommended Input Timing Requirements
Standard Mode
>0
f_SCL
SCL Clock Frequency
Fast Mode
>0
Standard Mode
4.7
t_LOW
SCL Low Period
Fast Mode
1.3
Standard Mode
4.0
t_HIGH
SCL High Period
Fast Mode
0.6
t_HD:STA
Hold time for a start or a repeated start ^{Standard Mode}
condition
Fast Mode
4.0
0.6
t_SU:STA
Set Up time for a start or a repeated
start condition
Standard Mode
Fast Mode
4.7
0.6
Standard Mode
0
t_HD:DAT Data Hold Time
Fast Mode
0
Standard Mode
250
t_SU:DAT Data Set Up Time
Fast Mode
100
Standard Mode
4.0
t_SU:STO Set Up Time for STOP Condition
Fast Mode
0.6
Standard Mode
4.7
t_BUF
Bus Free time between Stop and Start
Fast Mode
1.3
t_r
SCL & SDA Rise Time
Standard Mode
Fast Mode
t_f
SCL & SDA Fall Time
Standard Mode
Fast Mode
Typ
Max
Units
100
kHz
400
kHz
µs
µs
µs
µs
µs
µs
µs
µs
3.45
µs
900
ns
ns
ns
µs
µs
µs
µs
1000
ns
300
ns
300
ns
300
ns
Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I²C Compliant⁽¹⁾
Over recommended supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Recommended Input Timing Requirements
V_IH
Input High Level
SDA and SCL
0.7*V_DDIO
V_DDIO
Units
V
(1) Specification is ensured by design.
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