DS90UB913Q_13 Datasheet, PDF (34/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
SNLS420B – JULY 2012 – REVISED APRIL 2013
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Addr
(Hex)
0x1F
0x20
0x21
Name
Mode and OSS
Select
BCC Watchdog
Control
I²C Control 1
Table 2. DS90UB914Q Control Registers (continued)
Bits
Field
R/W
7
OEN_OSS
Override
RW
6 OEN Select
RW
5 OSS Select
R
4
MODE_OVERRID
E
RW
3
PIN_MODE_12–bit
HF mode
R
2
PIN_MODE_10 bit
mode
R
1
MODE_12–bit High
Frequency
RW
0
MODE_10–bit
mode
RW
7:1
BCC Watchdog
timer
RW
0
BCC Watchdog
Timer Disable
RW
7
I²C pass through
all
RW
6:4 I²C SDA Hold
RW
3:0 I²C Filter Depth
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
Allows overriding OEN and OSS select coming
from Pins
1: Overrides OEN/OSS_SEL selected by pins
0: Does NOT override OEN/OSS_SEL select
by pins
OEN configuration from register
OSS_SEL configuration from register
Allows overriding mode select bits coming from
back-channel
1: Overrides MODE select bits
0: Does not override MODE select bits
Status of mode select pin
Status of mode select pin
Selects 12 bit high frequency mode. This bit is
automatically updated by the mode settings
from RX unless MODE_OVERRIDE is SET
1: 12 bit high frequency mode is selected.
0: 12 bit high frequency mode is not selected.
Selects 10 bit mode. This bit is automatically
updated by the mode settings from RX unless
MODE_OVERRIDE is SET
1: Enables 10 bit mode.
0: Disables 10 bit mode.
The watchdog timer allows termination of a
control channel transaction if it fails to complete
within a programmed amount of time. This field
sets the Bidirectional Control Channel
Watchdog Timeout value in units of 2ms. This
field should not be set to 0.
Disable Bidirectional Control Channel
Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation
I2C Pass-Through All Transactions
0: Disabled
1: Enabled
Internal SDA Hold Time This field configures
the amount of internal hold time provided for
the SDA input relative to the SCL input. Units
are 50ns.
I²C Glitch Filter Depth This field configures the
maximum width of glitch pulses on the SCL and
SDA inputs that will be rejected. Units are 10ns.
34
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