DS90UB913Q_13 Datasheet, PDF (14/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
SNLS420B – JULY 2012 – REVISED APRIL 2013
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
t_RCP
Receiver Output
10–bit mode
PCLK (Figure 18)
Clock Period
12–bit high frequency mode
10
13.33
12–bit low frequency mode
10
t_PDC
PCLK Duty Cycle 10–bit mode
PCLK
45
12–bit high frequency mode
40
12–bit low frequency mode
40
t_CLH
LVCMOS Low-to- V_DDIO: 1.71V to 1.89V or 3.0V PCLK
High Transition Time to 3.6V,
1.3
t_CHL
LVCMOS High-to-
Low Transition Time
C_L = 8 pF (lumped load)
Default Registers
(Figure 16)⁽¹⁾
1.3
t_CLH
LVCMOS Low-to- V_DDIO: 1.71V to 1.89V or 3.0V ROUT[11:0], HS, VS
High Transition Time to 3.6V,
1
t_CHL
LVCMOS High-to-
Low Transition Time
C_L = 8 pF (lumped load)
Default Registers
(Figure 16)⁽¹⁾
1
t_ROS
ROUT Setup Data to V_DDIO: 1.71V to 1.89V or 3.0V ROUT[11:0], HS, VS
PCLK
to 3.6V,
t_ROH
ROUT Hold Data to
PCLK
C_L = 8 pF (lumped load)
Default Registers (Figure 18)
0.38T
0.38T
10–bit mode
154T
t_DD
Default Registers
12–bit low frequency
Deserializer Delay Register 0x03h b[0] (RRFB = 1) mode
109T
(Figure 17)⁽¹⁾
12–bit high frequency
mode
73T
t_DDLT
Deserializer Data
Lock Time
With Adaptive Equalization
(Figure 15)
10–bit mode
12–bit low frequency
mode
12–bit high frequency
mode
t_RCJ
Receiver Clock Jitter PCLK
SSCG[3:0] = OFF⁽¹⁾
10–bit mode
PCLK=100MHz
12–bit low frequency
mode
PCLK=50MHz
12–bit high frequency
mode
PCLK=75MHz
t_DPJ
Deserializer Period PCLK
Jitter
SSCG[3:0] = OFF⁽²⁾⁽¹⁾
10–bit mode
PCLK=100MHz
12–bit low frequency
mode
PCLK=50MHz
12–bit high frequency
mode
PCLK=75MHz
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Typ
50
50
50
2
2
2.5
2.5
0.5T
0.5T
15
15
15
20
22
45
170
180
300
Max
50
66.66
100
55
60
60
2.8
2.8
4
4
Units
ns
%
ns
ns
ns
158T
112T
ns
75T
22
22
ms
22
30
35
ps
90
815
330
ps
515
(1) Specification is ensured by characterization and is not tested in production.
(2) t_DPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
14
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