DS90UB913Q_13 Datasheet, PDF (36/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
SNLS420B – JULY 2012 – REVISED APRIL 2013
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Addr
(Hex)
Name
0x3C
Oscillator output
divider select
0x3D-
0x3E
0x3F
CML Output
Enable
0x40 SCL High Time
0x41 SCL Low Time
0x42 CRC Force Error
0x43-
0x4C
0x4D
AEQ Test Mode
Select
0x4E EQ Value
Table 2. DS90UB914Q Control Registers (continued)
Bits
Field
7:2 RSVD
R/W
Default
1:0
OSC OUT
DIVIDER SEL
RW
0
7:5 RSVD
4 CML OUT Enable
3:0 RSVD
RESERVED
RW
1
7:0 SCL High Time
RW
0x82
7:0 SCL Low Time
RW
0x82
7:2 RSVD
1
Force Back
Channel Error
Force One Back
0 Channel Error
7 RSVD
6 ^{AEQ Bypass}
5:0 RSVD
7:0
AEQ / Manual Eq
Readback
RW
0
RW
0
RESERVED
RW
0
R
0
Description
Reserved
Selects the divider for the OSC clock out on
PCLK when system is not locked and selected
by OEN/OSSSEL 0x02[5]
00: 50M (+/- 30%)
01: 25M (+/- 30%)
1X: 12.5M (+/- 30%)
Reserved
0: CML Loop-through Driver is powered up
1: CML Loop-through Driver is powered down.
Reserved
I²C Master SCL High Time This field configures
the high pulse width of the SCL output when
the De-Serializer is the Master on the local I²C
bus. Units are 50 ns for the nominal oscillator
clock frequency. The default value is set to
provide a minimum (4μs + 0.3μs of rise time for
cases where rise time is very fast) SCL high
time with the internal oscillator clock running at
26MHz rather than the nominal 20MHz.
I²C SCL Low Time This field configures the low
pulse width of the SCL output when the De-
Serializer is the Master on the local I²C bus.
This value is also used as the SDA setup time
by the I²C Slave for providing data prior to
releasing SCL during accesses over the
Bidirectional Control Channel. Units are 50 ns
for the nominal oscillator clock frequency. The
default value is set to provide a minimum
(4.7µs + 0.3µs of fall time for cases where fall
time is very fast) SCL low time with the internal
oscillator clock running at 26MHz rather than
the nominal 20MHz.
Reserved
1: This bit introduces multiple errors into Back
channel frame.
0: No effect
1: This bit introduces ONLY one error into Back
channel frame. Self clearing bit
0: No effect
Reserved
Bypass AEQ and use set manual EQ value
using register 0x04
Reserved
Read back the adaptive and manual
Equalization value
Table 3. Clock Sources for Forward Channel Frame on the Serializer During Normal Operation
DS90UB913Q
Reg 0x14 [2:1]
00
01
10
11
10–bit
Mode
50 MHz
100 MHz
50 MHz
25MHz
12–bit
High Frequency Mode
37.5 MHz
75 MHz
37.5 MHz
18.75 MHz
12–bit
Low Frequency Mode
25 MHz
50 MHz
25 MHz
12.5 MHz
36
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