DS90UB913Q_13 Datasheet, PDF (16/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
SNLS420B – JULY 2012 – REVISED APRIL 2013
www.ti.com
Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I²C Compliant⁽¹⁾ (continued)
Over recommended supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V_IL
V_HY
V_OL
I_IN
t_R
t_F
t_SU;DAT
t_HD;DAT
t_SP
C_IN
Input Low Level
Input Hysteresis
Output Low Level
Input Current
SDA Rise Time-READ
SDA Fall Time-READ
SDA and SCL
SDA, I_OL=0.5mA
SDA or SCL, V_IN=V_DDOP OR GND
SDA, RPU = 10kΩ, Cb ≤ 400pF
(Figure 4)
SeeFigure 4
SeeFigure 4
SDA or SCL
GND
0
—10
0.3*V_DDIO
V
>50
mV
0.4
V
10
µA
430
ns
20
ns
560
ns
615
ns
50
ns
<5
pF
AC Timing Diagrams and Test Circuits
SDA
t_f
SCL
t_LOW
t_r
START
t_HD;STA
t_HD;DAT
t_f
t_HIGH
t_HD;STA
t_BUF
t_r
t_SU;DAT
t_SU;STA
REPEATED
START
t_SU;STO
STOP START
Figure 4. Bi-directional Control Bus Timing
Device Pin Name
PCLK
(RFB = H)
D_IN/R_OUT
Signal Pattern
T
Figure 5. “Worst Case” Test Pattern
Vdiff
80%
20%
80%
Vdiff = 0V
20%
t_LHT
t_HLT
Vdiff = (D_OUT+) - (D_OUT-)
Figure 6. Serializer CML Output Load and Transition Times
D_OUT+
D_OUT-
100 nF
100 nF
Z_Diff = 100:
50:
100:
50:
SCOPE
BW 8 4.0 GHz
Figure 7. Serializer CML Output Load and Transition Times
16
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: DS90UB913Q DS90UB914Q