DS90UB913Q_13 Datasheet, PDF (13/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
www.ti.com
SNLS420B – JULY 2012 – REVISED APRIL 2013
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
t_LHT
CML Low-to-High Transition R_L = 100Ω (Figure 6)
Time
150
330
t_HLT
CML High-to-Low Transition R_L = 100Ω (Figure 6)
Time
150
330
t_DIS
Data Input Setup to PCLK Serializer Data Inputs
2
t_DIH
Data Input Hold from PCLK ^{(Figure 12)}
2
t_PLD
Serializer PLL Lock Time
R_L = 100Ω⁽¹⁾⁽²⁾, (Figure 13)
1
2
t_SD
Serializer Delay⁽²⁾
R_T = 100Ω
10–bit mode
Register 0x03h b[0] (TRFB = 1)
32.5T
38T
44T
(Figure 14)
R_T = 100Ω
12–bit mode
Register 0x03h b[0] (TRFB = 1)
11.75T
13T
15T
(Figure 14)
t_JIND
Serializer Output
Serializer output intrinsic deterministic
Deterministic Jitter
jitter . Measured (cycle-cycle) with
PRBS-7 test pattern⁽³⁾⁽⁴⁾
0.13
t_JINR
Serializer Output Random Serializer output intrinsic random jitter
Jitter
(cycle-cycle). Alternating-1,0
pattern. ^{(3) (4)}
0.04
t_JINT
Peak-to-peak Serializer
Serializer output peak-to-peak jitter
Output Jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measured (cycle-cycle) with
PRBS-7 test pattern.⁽³⁾⁽⁴⁾
0.396
λ_STXBW
Serializer Jitter Transfer
PCLK = 100MHz
Function -3 dB Bandwidth⁽⁵⁾ 10–bit mode. Default Registers
2.2
PCLK = 75MHz
2.2
12–bit high frequency mode. Default
Registers
PCLK = 50MHz
2.2
12–bit low frequency mode. Default
Registers
δ_STX
Serializer Jitter Transfer
Function (Peaking)⁽⁵⁾
PCLK = 100MHz
10–bit mode. Default Registers
1.06
PCLK = 75MHz
1.09
12–bit high frequency mode. Default
Registers
PCLK = 50MHz
1.16
12–bit low frequency mode. Default
Registers
δ_STXf
Serializer Jitter Transfer
Function (Peaking
PCLK = 100MHz
10–bit mode. Default Registers
400
Frequency) ⁽⁵⁾
PCLK = 75MHz
500
12–bit high frequency mode. Default
Registers
PCLK = 50MHz
600
12–bit low frequency mode. Default
Registers
Units
ps
ps
ns
ns
ms
ns
ns
UI
UI
UI
MHz
dB
kHz
(1) t_PLD and t_DDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
(2) Specification is ensured by design.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, T_A = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not specified.
(4) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
(5) Specification is ensured by characterization and is not tested in production.
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