DS90UB913Q_13 Datasheet, PDF (52/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
SNLS420B – JULY 2012 – REVISED APRIL 2013
APPLICATIONS INFORMATION
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AC COUPLING
The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme.
External AC coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in
Figure 43.
D_OUT+
D
D_OUT-
R_IN+
R
R_IN-
Figure 43. AC-Coupled Connection
For high-speed FPD–Link III transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s require a 100
nF AC coupling capacitors to the line.
Adaptive Equalizer – Loss Compensation
The adaptive equalizer is designed to compensate for signal degradation due to the differential insertion loss of
the interconnect components. There are limits to the amount of loss that can be compensated – these limits are
defined by the gain curve of the equalizer. In addition, there is an inherent tolerance for loss defined by the delta
between the serializer’s minimum VOD and the input threshold (Vswing) of the deserializer. In order to determine
the maximum cable reach, other factors that affect signal integrity such as jitter, skew, ISI, crosstalk, etc. need to
be taken into consideration. Figure 44 illustrates the maximum allowable interconnect loss with the adaptive
equalizer at its maximum gain setting (“914 equalizer gain”).
25
20
15
914 Equalizer Gain (dB)
VOD-Vswing Loss
10
Allowable Interconnect
Loss
5
0
100 200 300 400 500 600 700
SERIAL LINE FREQUENCY (MHz)
Figure 44. Adaptive Equalizer – Interconnect Loss Compensation
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