DS90UB913Q_13 Datasheet, PDF (2/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
SNLS420B – JULY 2012 – REVISED APRIL 2013
Typical Application Diagram
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Parallel
Data In
10 or 12
FPD-Link III
Parallel
Data Out
10 or 12
Megapixel
Imager/Sensor
2
HSYNC,
VSYNC
4
GPO
2
DS90UB913Q
Bidirectional
Control Bus Serializer
Bidirectional
Control Channel
DS90UB914Q
Deserializer
2
HSYNC,
VSYNC
4
GPIO
2
Bidirectional
Control Bus
DSP, FPGA/
µ -Processor/
ECU
Figure 1. Typical Application Circuit
Block Diagrams
10 or
12
DIN
HSYNC
VSYNC
4
GPO[3:0]
PCLK
PLL
Clock
Gen
R_T
R_{T DOUT+}
RIN0+ ^RT ^RT
DOUT-
RIN0-
RIN1+
CDR
Clock
Gen
PDB
Timing and
Control
SDA
SCL
ID[x]
MODE
DS90UB913Q - SERIALIZER
RIN1-
PDB
BISTEN
OEN
SEL
MODE
Timing and
Control
DS90UB914Q - DESERIALIZER
Figure 2. Block Diagram
10
or
12
ROUT
HSYNC
VSYNC
4
GPIO[3:0]
PCLK
LOCK
PASS
SDA
SCL
IDx[0]
IDx[1]
Image
Sensor
Camera Data
10 or 12
DATA
HSYNC
VSYNC
Pixel Clock
DS90UB913Q
Serializer
FPD-Link III
DS90UB914Q
Deserializer
DIN[11:0] or
DIN[9:0]
HSYNC,
VSYNC
PCLK
DOUT+
RIN+
DOUT-
RIN-
Bi-Directional
Control Channel
ROUT[11:0]
or
ROUT[9:0]
HSYNC,
VSYNC
PCLK
Camera Data
10 or 12
DATA
HSYNC
VSYNC
Pixel Clock
ECU Module
Camera Unit
4
GPO[3:0]
SDA
SCL
GPO[3:0]
SDA
SCL
GPIO[3:0]
SDA
SCL
4
GPIO[3:0]
SDA
SCL
Microcontroller
Figure 3. Application Block Diagram
2
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