DS90UB913Q_13 Datasheet, PDF (42/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
SNLS420B – JULY 2012 – REVISED APRIL 2013
www.ti.com
Bus Activity:
Master
SDA Line S
Slave
Address
7-bit Address 0
Register
Address
Data
P
Bus Activity:
Slave
A
A
A
C
C
C
K
K
K
Figure 29. Write Byte
Bus Activity:
Master
Slave
Address
Register
Address
Slave
Address
SDA Line S
7-bit Address 0
S
7-bit Address 1
Bus Activity:
Slave
A
A
A
C
C
C
K
K
K
Figure 30. Read Byte
Data
N
A
C
K
P
SDA
SCL
START
MSB
1
7-bit Slave Address
2
6
LSB
ACK
R/W
Direction
Bit
Acknowledge
from the Device
MSB
7
8
9
1
Data Byte
2
LSB N/ACK
*Acknowledge
or Not-ACK
8
9
Repeated for the Lower Data Byte
and Additional Data Transfers
STOP
Figure 31. Basic Operation
SDA
SCL
S
START condition, or
START repeat condition
P
STOP condition
Figure 32. Start and Stop Conditions
Slave Clock Stretching
The I2C compatible interface allows programming of the DS90UB913Q, DS90UB914Q, or an external remote
device (such as image sensor) through the bidirectional control To communicate and synchronize with remote
devices on the I2C bus through the bidirectional control channel/MCU, the chipset utilizes bus clock
stretching (holding the SCL line low) during data transmission; where the I2C slave pulls the SCL line low
on the 9th clock of every I2C transfer (before the ACK signal). The slave device will not control the clock and
only stretches it until the remote peripheral has responded. The I2C master must support clock stretching to
operate with the DS90UB913/914Q chipset.
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