DS90UB913Q_13 Datasheet, PDF (3/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

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DS90UB913Q, DS90UB914Q
SNLS420B – JULY 2012 – REVISED APRIL 2013
VDDIO
DIN[6]
DIN[7]
VDDD
DIN[8]
DIN[9]
DIN[10]
DIN[11]
24 23 22 21 20 19 18
17
DAP = GND
DS90UB913Q
32-Pin WQFN
(Top View)
1
2
3
4
5
6
7
8
GPO[1]
GPO[0]
VDDCML
DOUT+
DOUT-
VDDT
VDDPLL
PDB
Serializer - DS90UB913Q — Top View
DS90UB913Q SERIALIZER PIN DESCRIPTIONS
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
DIN[0:11]
19,20,21,22,
23,24,26,27,
29,30,31,32
Inputs,
LVCMOS
w/ pull down
Parallel Data Inputs.
HSYNC
1
Inputs,
Horizontal SYNC Input
LVCMOS
w/ pull down
VSYNC
2
Inputs,
Vertical SYNC Input
LVCMOS
w/ pull down
PCLK
3
Input, LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register.
w/ pull down
GENERAL PURPOSE OUTPUT (GPO)
GPO[1:0]
16,15
Output,
LVCMOS
General-purpose output pins can be configured as outputs; used to control and
respond to various commands. GPO[0:1] can be configured to be the outputs for input
signals coming from GPIO[0:1] pins on the Deserializer or can be configured to be
outputs of the local register on the Serializer.
GPO[2]/CLKOUT
17
Output,
LVCMOS
GPO2 pin can be configured to be the output for input signal coming from the GPIO2
pin on the Deserializer or can be configured to be the output of the local register on
the Serializer. It can also be configured to be the output clock pin when the
DS90UB913Q device is used in the External Oscillator mode. See Applications
Information for a detailed description of the DS90UB913/914Q chipsets working with
the external oscillator.
Copyright © 2012–2013, Texas Instruments Incorporated
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