DS90UB913Q_13 Datasheet, PDF (29/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
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Addr
(Hex)
0x03
Name
General
Configuration 1
0x04
EQ Feature
Control 1
0x05
0x06
SER ID
0x07
SER Alias
SNLS420B – JULY 2012 – REVISED APRIL 2013
Table 2. DS90UB914Q Control Registers (continued)
Bits
Field
R/W
7
RX Parity Checker
Enable
RW
6
TX CRC Checker
Enable
RW
5 V_DDIO Control
RW
4 V_DDIO Mode
RW
I²C Passthrough
3
RW
Default
1
1
1
0
1
2 AUTO ACK
RW
0
1 Parity Error Reset
RW
0
0 RRFB
RW
1
EQ level - when
AEQ bypass is
7:0 enabled EQ setting RW
is provided by this
register
0x00
RESERVED
7:1
Remote ID
RW
0x0C
RW
0
0 Freeze Device ID
7:1 Serializer Alias ID
RW
0x00
0 RSVD
Description
Forward Channel Parity Checker Enable
1: Enable
0: Disable
Back Channel CRC Generator Enable
1: Enable
0: Disable
Auto voltage control
1: Enable (auto detect mode)
0: Disable
VDDIO voltage set
1: 3.3V
0: 1.8V
I²C Pass-Through Mode
1: Pass-Through Enabled
0: Pass-Through Disabled
Automatically Acknowledge I²C Remote Write
When enabled, I²C writes to the Deserializer (or
any remote I²C Slave, if I²C PASS ALL is
enabled) are immediately acknowledged
without waiting for the Deserializer to
acknowledge the write. The accesses are then
remapped to address specified in 0x06. This
allows I2C bus without LOCK.
1: Enable
0: Disable
Parity Error Reset, This bit is self-clearing.
1: Parity Error Reset
0: No effect
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the
Falling Clock Edge.
0: Parallel Interface Data is strobed on the
Rising Clock Edge.
Equalization gain
0x00 = ~0.0 dB
0x01 = ~4.5 dB
0x03 = ~6.5 dB
0x07 = ~7.5 dB
0x0F = ~8.0 dB
0x1F = ~11.0 dB
0x3F = ~12.5 dB
Remote Serializer ID
Freeze Serializer Device ID Prevent auto-
loading of the Serializer Device ID from the
Forward Channel. The ID will be frozen at the
value written.
7-bit Remote Serializer Device Alias ID
Configures the decoder for detecting
transactions designated for an I²C Deserializer
device. The transaction will be remapped to the
address specified in the SER ID register. A
value of 0 in this field disables access to the
remote I²C Slave.
Reserved
Copyright © 2012–2013, Texas Instruments Incorporated
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