DS90UB913Q_13 Datasheet, PDF (54/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
SNLS420B – JULY 2012 – REVISED APRIL 2013
Figure 46 shows a typical connection of the DS90UB914Q Deserializer.
DS90UB914Q (Des)
1.8V
VDDIO
VDDD
C3
C11
VDDIO1
C8 C16
C18
VDDR
C4
C12
1.8V
FB1
1.8V
FB2
Serial
FPD-Link II
Interface
1.8V
10 k:
RMODE
I2C
Bus
Interface
VDDSSCG
C5
C13
C6 C14
VDDPLL
C17
C7 C15
VDDCML
C19
C1
C2
C1
C2
VDDIO
RIN1+
RIN1-
RIN0+
RIN0-
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
MODE
PDB
SEL
OEN
OSS_SEL
BISTEN
FB3
FB4
Optional
RPU
C20
RPU
SCL
SDA
C21
Optional
RES_PIN43
DAP (GND)
VDDIO2
C9
VDDIO3
C10
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
HS
VS
PCLK
LOCK
PASS
IDx[0]
LVCMOS
Parallel
Outputs
1.8V
10 k:
RID0
1.8V
IDx[1]
10 k:
RID1
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C10 = 0.01 PF
C11 - C16 = 0.1 PF
C17 - C18 = 4.7 PF
C19 = 22 PF
C20 - C21 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB4: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Figure 46. DS90UB914Q Typical Connection Diagram — Pin Control
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