DS90UB913Q_13 Datasheet, PDF (28/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
SNLS420B – JULY 2012 – REVISED APRIL 2013
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Addr
(Hex)
0x01
0x02
Name
Reset
General
Configuration 0
Table 2. DS90UB914Q Control Registers (continued)
Bits
Field
R/W
7:6 RSVD
5 ANAPWDN
RW
4:2 RSVD
1 Digital Reset 1
RW
0 Digital Reset 0
RW
7 RSVD
6 RSVD
5 Auto-Clock
RW
4 SSCG LFMODE
RW
3:0 SSCG
RW
Default
0
0
0
0
0
0
Description
Reserved
This register can be set only through local I²C
access
1: Analog power-down : Powers Down the
analog block in the Serializer
0: No effect
Reserved
Digital Reset Resets the entire digital block
except registers. This bit is self-clearing.
1: Reset
0: No effect
Digital Reset Resets the entire digital block
including registers. This bit is self-clearing.
1: Reset
0: No effect
Reserved
Reserved
1: Output PCLK or OSC clock when not
LOCKED
0: Only PCLK
1: Selects 8x mode for 10-18 MHz frequency
range in SSCG
0: SSCG running at 4X mode
SSCG Select
0000: Normal Operation, SSCG OFF
0001: fmod (kHz) PCLK/2168, fdev +/-0.50%
0010: fmod (kHz) PCLK/2168, fdev +/-1.00%
0011: fmod (kHz) PCLK/2168, fdev +/-1.50%
0100: fmod (kHz) PCLK/2168, fdev +/-2.00%
0101: fmod (kHz) PCLK/1300, fdev +/-0.50%
0110: fmod (kHz) PCLK/1300, fdev +/-1.00%
0111: fmod (kHz) PCLK/1300, fdev +/-1.50%
1000: fmod (kHz) PCLK/1300, fdev +/-2.00%
1001: fmod (kHz) PCLK/868, fdev +/-0.50%
1010: fmod (kHz) PCLK/868, fdev +/-1.00%
1011: fmod (kHz) PCLK/868, fdev +/-1.50%
1100: fmod (kHz) PCLK/868, fdev +/-2.00%
1101: fmod (kHz) PCLK/650, fdev +/-0.50%
1110: fmod (kHz) PCLK/650, fdev +/-1.00%
1111: fmod (kHz) PCLK/650, fdev +/-1.50%
Note: This regsiter should be changed only
after disabling SSCG.
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