DS90UB913Q_13 Datasheet, PDF (35/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
www.ti.com
SNLS420B – JULY 2012 – REVISED APRIL 2013
Addr
(Hex)
Name
0x22
I²C Control 2
0x23
General Purpose
Control
0x24
BIST Control
0x25 Parity Error Count
0x26–0
x3B
Table 2. DS90UB914Q Control Registers (continued)
Bits
Field
R/W
Default
7
Forward Channel
Sequence Error
R
0
6
Clear Sequence
Error
RW
0
5 RSVD
4:3 SDA Output Delay RW
0
2 Local Write Disable RW
0
1
I²C Bus Timer
Speedup
RW
0
0
I²C Bus Timer
Disable
RW
0
7:0 GPCR
7:4 RSVD
RW
0
3
BIST Pin
Configuration
RW
1
2:1 BIST Clock Source RW
00
0 BIST Enable
RW
0
7:0 BIST Error Count
R
0
RESERVED
Description
Control Channel Sequence Error Detected This
bit indicates a sequence error has been
detected in forward control channel.
1: If this bit is set, an error may have occurred
in the control channel operation
0: No forward channel errors have been
detected on the control channel
Clears the Sequence Error Detect bit
Reserved
SDA Output Delay This field configures output
delay on the SDA output. Setting this value will
increase output delay in units of 50ns. Nominal
output delay values for SCL to SDA are:
00 : 350ns
01: 400ns
10: 450ns
11: 500ns
Disable Remote Writes to local registers
Setting this bit to a 1 will prevent remote writes
to local device registers from across the control
channel. This prevents writes to the
Deserializer registers from an I2C master
attached to the Serializer. Setting this bit does
not affect remote access to I2C slaves at the
Deserializer.
Speed up I²C Bus Watchdog Timer
1: Watchdog Timer expires after approximately
50µs
0: Watchdog Timer expires after approximately
1s.
Disable I²C Bus Watchdog Timer When the I²C
Watchdog Timer may be used to detect when
the I²C bus is free or hung up following an
invalid termination of a transaction. If SDA is
high and no signaling occurs for approximately
1 second, the I²C bus will assumed to be free.
If SDA is low and no signaling occurs, the
device will attempt to clear the bus by driving 9
clocks on SCL
Scratch Register
Reserved
Bist Configured through Pin.
1: Bist configured through pin.
0: Bist configured through register bit
"reg_24[0]"
BIST Clock Source
See Table 4
BIST Control
1: Enabled
0: Disabled
Number of Forward channel Parity errors in the
BIST mode.
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