DS90UB913Q_13 Datasheet, PDF (1/63 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB913Q, DS90UB914Q
www.ti.com
SNLS420B – JULY 2012 – REVISED APRIL 2013
DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and
Deserializer with Bidirectional Control Channel
Check for Samples: DS90UB913Q, DS90UB914Q
FEATURES
1
•2 10 MHz to 100 MHz Input Pixel Clock Support
• Single Differential Pair Interconnect
• Programmable Data Payload:
– 10 bit Payload up to 100Mhz
– 12 bit Payload up to 75MHz
• Continuous Low Latency Bidirectional Control
Interface Channel with I²C support@400kHz
• 2:1 Multiplexer to Choose Between Two Input
Imagers
• Embedded Clock With DC Balanced Coding to
Support AC-Coupled Interconnects
• Capable of Driving up to 25 Meters Shielded
Twisted-pair
• Receive Equalizer Automatically Adapts for
Changes in Cable Loss
• 4 Dedicated General Purpose Input (GPI)/
Output (GPO)
• LOCK Output Reporting Pin and AT-SPEED
BIST Diagnosis Feature to Validate Link
Integrity
• 1.8V, 2.8V or 3.3V Compatible Parallel Inputs
on Serializer
• Single Power Supply at 1.8V
• ISO 10605 and IEC 61000-4-2 ESD Compliant
• Automotive Grade Product: AEC-Q100 Grade 2
Qualified
• Temperature Range −40°C to +105°C
• Small Serializer Footprint (5mm x 5mm)
• EMI/EMC Mitigation - Deserializer
– Programmable Spread Spectrum (SSCG)
Outputs.
– Receiver Staggered Outputs
DESCRIPTION
The DS90UB913Q/DS90UB914Q chipset offers a
FPD-Link III interface with a high-speed forward
channel and a bidirectional control channel for data
transmission over a single differential pair. The
DS90UB913Q/914Q chipsets incorporate differential
signaling on both the high-speed forward channel and
bidirectional control channel data paths. The
Serializer/ Deserializer pair is targeted for
connections between imagers and video processors
in an ECU (Electronic Control Unit). This chipset is
ideally suited for driving video data requiring up to 12
bit pixel depth plus two synchronization signals along
with bidirectional control channel bus.
There is a multiplexer at the Deserializer to choose
between two input imagers. The Deserializer can
have only one active input imager. The primary video
transport converts 10/12 bit data over a single high-
speed serial stream, along with a separate low
latency bidirectional control channel transport that
accepts control information from an I2C port and is
independent of video blanking period.
Using TI’s embedded clock technology allows
transparent full-duplex communication over a single
differential pair, carrying asymmetrical bidirectional
control channel information in both directions. This
single serial stream simplifies transferring a wide data
bus over PCB traces and cable by eliminating the
skew problems between parallel data and clock
paths. This significantly saves system cost by
narrowing data paths that in turn reduce PCB layers,
cable width, and connector size and pins. In addition,
the Deserializer inputs provide adaptive equalization
to compensate for loss from the media over longer
distances. Internal DC balanced encoding/decoding is
used to support AC-Coupled interconnects. The
Serializer is offered in a 32-pin WQFN package and
the Deserializer is offered in a 48-pin WQFN
package.
APPLICATIONS
• Front or Rear View Camera for Collision
Mitigation
• Surround View for Parking Assistance
1
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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