S71GL032A Datasheet, PDF (98/102 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory and RAM

Advance Information
Data Retention Characteristics (4M Version G)
Item
Symbol
Test Condition
Min Typ Max Unit
V_CC for data retention
V_DR CS1# ≥ V_CC-0.2V (Note 1), V_IN ≥ 0V. BYTE# = V_SS or V_CC 1.5
-
3.3 V
Data retention current
I_DR V_CC=1.5V, CS1# ≥ V_CC-0.2V (Note 1), V_IN ≥ 0V
-
-
3 µA
Data retention set-up time t_SDR
See data retention waveform
Recovery time
t_RDR
0
-
t_RC
-
-
ns
-
Notes:
1. CS1 controlled:CS1#≥ V_CC-0.2V. CS2 controlled: CS2 ≤ 0.2V.
Data Retention Characteristics (8M Version C)
Item
Symbol
Test Condition
V_CC for data retention
Data retention current
Data retention set-up time
Recovery time
V_DR
I_DR
t_SDR
t_RDR
CS1# ≥ V_CC-0.2V (Note 1). BYTE# = V_SS or V_CC
V_CC=3.0V, CS1# ≥ V_CC-0.2V (Note 1)
See data retention waveform
Notes:
1. CS1 controlled:CS1#≥ V_CC-0.2V. CS2 controlled: CS2 ≤ 0.2V.
Data Retention Characteristics (8M Version D)
Min Typ Max Unit
1.5
-
3.3 V
-
-
15 µA
0
-
t_RC
-
-
ns
-
Item
Symbol
Test Condition
V_CC for data retention
Data retention current
Data retention set-up time
Recovery time
V_DR
I_DR
t_SDR
t_RDR
CS1# ≥ V_CC-0.2V (Note 1), BYTE# = V_SS or V_CC
V_CC=3.0V, CS1# ≥ V_CC-0.2V (Note 1)
See data retention waveform
Notes:
1. CS1 controlled:CS1#≥ V_CC-0.2V. CS2 controlled: CS2 ≤ 0.2V.
Min Typ Max Unit
1.5
-
3.3 V
-
-
TBD µA
0
-
t_RC
-
-
ns
-
Timing Diagrams
Address
tRC
tAA
tOH
Data Out
Previous Data Valid
Data Valid
Figure 33. Timing Waveform of Read Cycle(1) (Address Controlled, CS#1=OE#=V_IL, CS2=WE#=V_IH, UB#
and/or LB#=V_IL)
98
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005