S71GL032A Datasheet, PDF (100/102 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory and RAM

Advance Information
Address
CS1#
CS2
UB#, LB#
WE#
Data in
tAS(3)
tWC
tCW(2)
tAW
tWR(4)
tBW
tWP(1)
tDW
tDH
Data Valid
Data out
High-Z
High-Z
Figure 36. Timing Waveform of Write Cycle(2) (CS# controlled, if BYTE# is Low, Ignore UB#/LB# Timing)
Address
CS1#
CS2
UB#, LB#
WE#
Data in
tAS(3)
tWC
tCW(2)
tAW
tCW(2)
tBW
tWP(1)
tWR(4)
tDW
tDH
Data Valid
Data out
High-Z
High-Z
Notes:
1. A write occurs during the overlap (t_WP) of low CS1# and low WE#. A write begins when CS1# goes low and WE#
goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double
byte operation. A write ends at the earliest transition when CS1# goes high and WE# goes high. The t_WP is
measured from the beginning of write to the end of write.
2. t_CW is measured from the CS1# going low to the end of write.
3. t_AS is measured from the address valid to the beginning of write.
4. t_WR is measured from the end of write to the address change. t_WR applied in case a write ends as CS1# or WE#
going high.
Figure 37. Timing Waveform of Write Cycle(3) (UB#, LB# controlled)
100
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005