S71GL032A Datasheet, PDF (56/102 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory and RAM

Advance Information
Command Definitions
Command
Sequence
(Note 1)
Read (Note 6)
Reset (Note 7)
Manufacturer ID
Device ID (Note 9)
Secured Silicon Sector Factory
Protect (Note 10)
Table 22. Command Definitions (x16 Mode)
Bus Cycles (Notes 2–5)
First
Second
Third
Fourth
Addr Data Addr Data Addr Data Addr
Data
1 RA RD
1 XXX F0
4 555 AA
2AA
55
555
90
X00
0001
4 555 AA
2AA
55
555
90
X01
227E
Fifth
Sixth
Addr Data Addr Data
X0E
X0F
4 555 AA
2AA
55
555
90
X03 (Note 10)
Sector Group Protect Verify (Note
12)
4
555
AA
2AA
55
555
90 (SA)X02 00/01
Enter Secured Silicon Sector Region
Exit Secured Silicon Sector Region
Program
Write to Buffer (Note 11)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 13)
Unlock Bypass
Unlock Bypass Program (Note 14)
Unlock Bypass Reset (Note 15)
Chip Erase
Sector Erase
Program/Erase Suspend (Note 16)
Program/Erase Resume (Note 17)
CFI Query (Note 18)
3 555 AA 2AA
55
555
88
4 555 AA
2AA
55
555
90
XXX
4 555 AA 2AA
55
555
A0
PA
3 555 AA
2AA
55
SA
25
SA
1 SA
29
3 555 AA 2AA
55
555
F0
3 555 AA 2AA
55
555
20
2 XXX A0
PA
PD
2 XXX 90
XXX
00
6 555 AA 2AA
55
555
80
555
6 555 AA 2AA
55
555
80
555
1 XXX B0
1 XXX 30
1 55
98
00
PD
WC
PA
PD WBL PD
AA
2AA 55 555 10
AA
2AA 55
SA
30
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or
CE# pulse, whichever happens later.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when lower address bits are
555 or 2AA as shown in table, address bits above A11 and data
bits above DQ7 are don’t care.
5. No unlock or command cycles required when device is in read
mode.
6. Reset command is required to return to read mode (or to erase-
suspend-read mode if previously in Erase Suspend) when device
is in autoselect mode, or if DQ5 goes high while device is
providing status information.
7. Fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. Except for RD, PD
and WC. See Autoselect Command Sequence section for more
information.
8. Device ID must be read in three cycles.
9. If WP# protects highest address sector, data is 98h for factory
locked and 18h for not factory locked. If WP# protects lowest
address sector, data is 88h for factory locked and 08h for not
factor locked.
PD = Program Data for location PA. Data latches on rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
10. Data is 00h for an unprotected sector group and 01h for a
protected sector group.
11. Total number of cycles in command sequence is determined by
number of words written to write buffer. Maximum number of
cycles in command sequence is 21, including “Program Buffer to
Flash” command.
12. Command sequence resets device for next command after
aborted write-to-buffer operation.
13. Unlock Bypass command is required prior to Unlock Bypass
Program command.
14. Unlock Bypass Reset command is required to return to read
mode when device is in unlock bypass mode.
15. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Erase Suspend mode. Erase Suspend
command is valid only during a sector erase operation.
16. Erase Resume command is valid only during Erase Suspend
mode.
17. Command is valid when device is ready to read array data or
when device is in autoselect mode.
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S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005