S71GL032A Datasheet, PDF (84/102 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory and RAM

Advance Information
Table 26. Switching Characteristics
Parameter
Description
Read Cycle
t_RC
Read Cycle Time
t_AA
Address to Data Valid
t_OHA
Data Hold from Address Change
t_ACE
CE#1 Low and CE2 High to Data Valid
t_DOE
OE# Low to Data Valid
t_LZOE
OE# Low to Low Z (note 2, 3)
t_HZOE
OE# High to High Z (note 2, 3)
t_LZCE
CE#1 Low and CE2 High to Low Z (note 2, 3)
t_HZCE
CE#1 High and CE2 Low to High Z (note 2, 3)
t_DBE
BHE# / BLE# Low to Data Valid
t_LZBE
BHE# / BLE# Low to Low Z (note 2, 3)
t_HZBE
BHE# / BLE# High to High Z (note 2, 3)
t_SK (note 4)
Address Skew
Write Cycle (note 5)
t_WC
t_SCE
t_AW
t_HA
t_SA
t_PWE
t_BW
t_SD
t_HD
t_HZWE
t_LZWE
Write Cycle Time
CE#1 Low an CE2 High to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE# Pulse Width
BLE# / BHE# LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE# Low to High Z (note 2, 3)
WE# High to Low Z (note 2, 3)
Min Max Unit
70
70
10
70
35
5
25
ns
5
25
70
5
25
10
70
55
55
0
0
55
ns
55
25
0
25
5
Notes:
1. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of V_CC(typ.) /2, input pulse levels of
0 to V_CC(typ.), and output loading of the specified I_OL/I_OH and 30 pF load capacitance.
2. t_HZOE, t_HZCE, t_HZBE and t_HZWE transitions are measured when the outputs enter a high-impedance state.
3. High-Z and Low-Z parameters are characterized and are not 100% tested.
4. To achieve 55-ns performance, the read access should be CE# controlled. In this case t_ACE is the critical parameter and t_SK is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
5. The internal write time of the memory is defined by the overlap of WE#, CE#1 = V_IL, CE2 = V_IH, B_HE and/or B_LE =V_IL. All
signals must be Active to initiate a write and any of these signals can terminate a write by going Inactive. The data input set-
up and hold timing should be referenced to the edge of the signal that terminates write.
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S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005