S71GL032A Datasheet, PDF (87/102 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory and RAM

Advance Information
ADDRESS
CE#1
CE₂
WE#
BHE#/BLE#
t_WC
t_SCE
t_SA
t_AW
t_HA
t_PWE
t_BW
OE#
DATA I/O
DON’T CARE
t_HZOE
Figure 29.
t_SD
t_HD
VALID DATA
Write Cycle 2 (CE#1 or CE2 Controlled)
Notes:
1. High-Z and Low-Z parameters are characterized and are not 100% tested.
2. The internal write time of the memory is defined by the overlap of WE#, CE#1 = V_IL, CE2 = V_IH, B_HE and/or B_LE =V_IL. All
signals must be Active to initiate a write and any of these signals can terminate a write by going Inactive. The data input set-
up and hold timing should be referenced to the edge of the signal that terminates write.
3. Data I/O is high impedance if OE# ≥ V_IH.
4. If Chip Enable goes Inactive simultaneously with WE# = High, the output remains in a high-impedance state.
5. During the Don’t Care period in the Data I/O waveform, the I/Os are in output state and input signals should not be applied.
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
87