S71GL032A Datasheet, PDF (85/102 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory and RAM

Advance Information
Switching Waveforms
t_RC
ADDRESS
DATA OUT
t_SK
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
Figure 26. Read Cycle 1 (Address Transition Controlled)
Notes:
1. To achieve 55-ns performance, the read access should be CE# controlled. In this case t_ACE is the critical parameter and t_SK is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
2. Device is continuously selected. OE#, CE# = V_IL.
3. WE# is High for Read Cycle.
ADDRESS
CE#1
t_SK
t_RC
CE₂
BHE#/BLE#
OE#
DATA OUT
t_ACE
t_LZBE
t_DBE
t_DOE
t_LZOE
HIGH IMPEDENCE
t_LZCE
t_HZCE
t_HZBE
t_HZOE
DATA VALID
HIGH
IMPEDENCE
Figure 27. Read Cycle 2 (OE# Controlled)
Notes:
1. To achieve 55-ns performance, the read access should be CE# controlled. In this case t_ACE is the critical parameter and t_SK is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
2. WE# is High for Read Cycle.
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
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