S71GL032A Datasheet, PDF (39/102 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory and RAM

Advance Information
Low V_CC Write Inhibit
When V_CC is less than V_LKO, the device does not accept any write cycles. This pro-
tects data during V_CC power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets to the read
mode. Subsequent writes are ignored until V_CC is greater than V_LKO. The system
must provide the proper signals to the control pins to prevent unintentional writes
when V_CC is greater than V_LKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V_IL, CE# = V_IH or WE# =
V_IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V_IL and OE# = V_IH during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
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