LAN9313 Datasheet, PDF (48/398 Pages) SMSC Corporation – Three Port 10/100 Managed Ethernet Switch with MII

STRAP NAME
autoneg_strap_2
speed_strap_2
duplex_strap_2
Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
Table 4.2 Soft-Strap Configuration Strap Definitions (continued)
DESCRIPTION
PIN / DEFAULT
VALUE
Port 2 Auto Negotiation Enable Strap: Configures the
default value for the Auto-Negotiation (PHY_AN) enable bit
in the PHY_BASIC_CTRL_2 register (See
Section 13.2.2.1). When configured low, auto-negotiation is
disabled. When configured high, auto-negotiation is
enabled.
AUTO_NEG_2
This strap also affects the default value of the following bits:
„ PHY_SPEED_SEL_LSB and PHY_DUPLEX bits of the
Port x PHY Basic Control Register
(PHY_BASIC_CONTROL_x)
„ 10BASE-T Full Duplex (bit 6) and 10BASE-T Half Duplex
(bit 5) bits of the Port x PHY Auto-Negotiation
Advertisement Register (PHY_AN_ADV_x)
„ MODE[2:0] bits of the Port x PHY Special Modes Register
(PHY_SPECIAL_MODES_x)
Refer to the respective register definition sections for
additional information.
Port 2 Speed Select Strap: Configures the default value
for the Speed Select LSB (PHY_SPEED_SEL_LSB) bit in
the PHY_BASIC_CTRL_2 register (See Section 13.2.2.1).
When configured low, 10 Mbps is selected. When
configured high, 100 Mbps is selected.
SPEED_2
This strap also affects the default value of the following bits:
„ PHY_SPEED_SEL_LSB bit of the Port x PHY Basic
Control Register (PHY_BASIC_CONTROL_x)
„ 10BASE-T Full Duplex (bit 6) and 10BASE-T Half Duplex
(bit 5) bits of the Port x PHY Auto-Negotiation
Advertisement Register (PHY_AN_ADV_x)
„ MODE[2:0] bits of the Port x PHY Special Modes Register
(PHY_SPECIAL_MODES_x)
Refer to the respective register definition sections for
additional information.
Port 2 Duplex Select Strap: Configures the default value
for the Duplex Mode (PHY_DUPLEX) bit in the
PHY_BASIC_CTRL_2 register (See Section 13.2.2.1).
When configured low, half-duplex is selected. When
configured high, full-duplex is selected.
DUPLEX_2
This strap also affects the default value of the following bits:
„ PHY_DUPLEX bit of the Port x PHY Basic Control
Register (PHY_BASIC_CONTROL_x)
„ 10BASE-T Full Duplex (bit 6) of the Port x PHY Auto-
Negotiation Advertisement Register (PHY_AN_ADV_x)
„ MODE[2:0] bits of the Port x PHY Special Modes Register
(PHY_SPECIAL_MODES_x)
Refer to the respective register definition sections for
additional information.
Revision 1.2 (04-08-08)
48
DATASHEET
SMSC LAN9313/LAN9313i