LAN9313 Datasheet, PDF (267/398 Pages) SMSC Corporation – Three Port 10/100 Managed Ethernet Switch with MII

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
13.3.1.4 Switch Global Interrupt Pending Register (SW_IPR)
Register #:
0005h
Size:
32 bits
This read-only register contains the pending global interrupts for the switch fabric. A set bit indicates
an unmasked bit in the corresponding switch fabric sub-system has been triggered. All switch related
interrupts in this register may be masked via the Switch Global Interrupt Mask Register (SW_IMR)
register. When an unmasked switch fabric interrupt is generated in this register, the interrupt will trigger
the SWITCH_INT bit in the Interrupt Status Register (INT_STS). Refer to Chapter 5, "System
Interrupts," on page 52 for more information.
BITS
DESCRIPTION
31:7 RESERVED
6 Buffer Manager Interrupt (BM)
Set when any unmasked bit in the Buffer Manager Interrupt Pending
Register (BM_IPR) is triggered. This bit is cleared upon a read.
5 Switch Engine Interrupt (SWE)
Set when any unmasked bit in the Switch Engine Interrupt Pending Register
(SWE_IPR) is triggered. This bit is cleared upon a read.
4:3 RESERVED
2 Port 2 MAC Interrupt (MAC_2)
Set when any unmasked bit in the MAC_IPR_2 register (see Section
13.3.2.44, on page 311) is triggered. This bit is cleared upon a read.
1 Port 1 MAC Interrupt (MAC_1)
Set when any unmasked bit in the MAC_IPR_1 register (see Section
13.3.2.44, on page 311) is triggered. This bit is cleared upon a read.
0 Port 0 MAC Interrupt (MAC_MII)
Set when any unmasked bit in the MAC_IPR_MII register (see Section
13.3.2.44, on page 311) is triggered. This bit is cleared upon a read.
TYPE
RO
RC
RC
RO
RC
RC
RC
DEFAULT
-
0b
0b
-
0b
0b
0b
SMSC LAN9313/LAN9313i
267
DATASHEET
Revision 1.2 (04-08-08)