LAN9313 Datasheet, PDF (219/398 Pages) SMSC Corporation – Three Port 10/100 Managed Ethernet Switch with MII

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
BITS
DESCRIPTION
7 100BASE-X Half Duplex
This bit indicates the emulated link partner PHY 100BASE-X half duplex
capability.
0: 100BASE-X half duplex ability not supported
1: 100BASE-X half duplex ability supported
6 10BASE-T Full Duplex
This bit indicates the emulated link partner PHY 10BASE-T full duplex
capability.
0: 10BASE-T full duplex ability not supported
1: 10BASE-T full duplex ability supported
5 10BASE-T Half Duplex
This bit indicates the emulated link partner PHY 10BASE-T half duplex
capability.
0: 10BASE-T half duplex ability not supported
1: 10BASE-T half duplex ability supported
4:0 Selector Field
This field identifies the type of message being sent by Auto-Negotiation.
00001: IEEE 802.3
TYPE
RO
DEFAULT
Note 13.38
RO
Note 13.38
RO
Note 13.38
RO
00001b
Note 13.35 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
Note 13.36 The emulated link partner does not support next page, always instantly sends its link code
word, never sends a fault, and does not support 100BASE-T4.
Note 13.37 The emulated link partner’s asymmetric/symmetric pause ability is based upon the values
of the Asymmetric Pause and Pause bits of the Virtual PHY Auto-Negotiation
Advertisement Register (VPHY_AN_ADV). Thus the emulated link partner always
accommodates the request of the Virtual PHY, as shown in Table 13.5. See Section 7.3.1,
"Virtual PHY Auto-Negotiation," on page 98 for additional information.
Table 13.5 Emulated Link Partner Pause Flow Control Ability Default Values
VPHY Symmetric
Pause
(register 4.10)
VPHY Asymmetric
Pause
(register 4.11)
No Flow Control Enabled
0
0
Symmetric Pause
1
0
Asymmetric Pause Towards
0
1
Switch
Asymmetric Pause Towards MAC
1
1
Link Partner
Symmetric Pause
(register 5.10)
0
1
1
0
Link Partner
Asymmetric Pause
(register 5.11)
0
0
1
1
Note 13.38 The emulated link partner’s ability is based on the MII_DUPLEX pin, duplex_pol_strap_mii,
and speed_strap_mii, as well as on the Auto-Negotiation success. Table 13.6 defines the
default capabilities of the emulated link partner as a function of these signals. Configuration
strap values are latched upon the de-assertion of a chip-level reset as described in Section
4.2.4, "Configuration Straps," on page 45. For more information on the Virtual PHY auto-
negotiation, see Section 7.3.1, "Virtual PHY Auto-Negotiation," on page 98.
SMSC LAN9313/LAN9313i
219
DATASHEET
Revision 1.2 (04-08-08)