LAN9313 Datasheet, PDF (186/398 Pages) SMSC Corporation – Three Port 10/100 Managed Ethernet Switch with MII

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
BITS
22
21
20
19
18
17
16
15
14
DESCRIPTION
Primary MAC Address Enable Port 1 (MAC_PRI_EN_1)
This bit enables/disables the primary MAC address on Port 1.
0: Disables primary MAC address on Port 1
1: Enables MAC address 01:00:5E:00:01:81 as a PTP address on Port 1
Alternate MAC Address 1 Enable Port 1 (MAC_ALT1_EN_1)
This bit enables/disables the alternate MAC address 1 on Port 1.
0: Disables alternate MAC address on Port 1
1: Enables MAC address 01:00:5E:00:01:82 as a PTP address on Port 1
Alternate MAC Address 2 Enable Port 1 (MAC_ALT2_EN_1)
This bit enables/disables the alternate MAC address 2 on Port 1.
0: Disables alternate MAC address on Port 1
1: Enables MAC address 01:00:5E:00:01:83 as a PTP address on Port 1
Alternate MAC Address 3 Enable Port 1 (MAC_ALT3_EN_1)
This bit enables/disables the alternate MAC address 3 on Port 1.
0: Disables alternate MAC address on Port 1
1: Enables MAC address 01:00:5E:00:01:84 as a PTP address on Port 1
User Defined MAC Address Enable Port 1 (MAC_USER_EN_1)
This bit enables/disables the auxiliary MAC address on Port 1. The auxiliary
address is defined via the 1588_AUX_MAC_HI and 1588_AUX_MAC_LO
registers.
0: Disables auxiliary MAC address on Port 1
1: Enables auxiliary MAC address as a PTP address on Port 1
Lock Enable RX Port 1 (LOCK_RX_1)
This bit enables/disables the RX lock. This lock prevents a 1588 capture
from overwriting the Clock, UUDI and Sequence ID values if the 1588 RX
interrupt for Port 1 is ready set due to a previous capture.
0: Disables RX Port 1 Lock
1: Enables RX Port 1 Lock
Lock Enable TX Port 1 (LOCK_TX_1)
This bit enables/disables the TX lock. This lock prevents a 1588 capture
from overwriting the Clock, UUDI and Sequence ID values if the 1588 TX
interrupt for Port 1 is ready set due to a previous capture.
0: Disables TX Port 1 Lock
1: Enables TX Port 1 Lock
Master/Slave Port 0(External MII)(M_nS_MII)
When set, Port 0 is a time clock master and captures timestamps when a
Sync packet is transmitted and when a Delay_Req is received. When
cleared, Port 0 is a time clock slave and captures timestamps when a
Delay_Req packet is transmitted and when a Sync packet is received.
Note: For Port 0, receive is defined as data from the switch fabric, while
transmit is defined as data to the switch fabric.
Primary MAC Address Enable Port 0(External MII) (MAC_PRI_EN_MII)
This bit enables/disables the primary MAC address on Port 0.
0: Disables primary MAC address on Port 0
1: Enables MAC address 01:00:5E:00:01:81 as a PTP address on Port 0
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DEFAULT
1b
0b
0b
0b
0b
1b
1b
0b
1b
Revision 1.2 (04-08-08)
186
DATASHEET
SMSC LAN9313/LAN9313i