LAN9313 Datasheet, PDF (20/398 Pages) SMSC Corporation – Three Port 10/100 Managed Ethernet Switch with MII

2.2.1
2.2.2
Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
System Clocks/Reset/PME Controller
A clock module contained within the LAN9313/LAN9313i generates all the system clocks required by
the device. This module interfaces directly with the external 25MHz crystal/oscillator to generate the
required clock divisions for each internal module, with the exception of the 1588 clocks, which are
generated in the 1588 Time Stamp Clock/Events module. A 16-bit general purpose timer and 32-bit
free-running clock are provided by this module for general purpose use. The Port 1 & 2 PHYs provide
general power-down and energy detect power-down modes, which allow a reduction in PHY power
consumption.
The LAN9313/LAN9313i reset events are categorized as chip-level resets, multi-module resets, and
single-module resets.
A chip-level reset is initiated by assertion of any of the following input events:
„ Power-On Reset
„ nRST Pin Reset
A multi-module reset is initiated by assertion of the following:
„ Digital Reset - DIGITAL_RST (bit 0) in the Reset Control Register (RESET_CTL)
- Resets all LAN9313/LAN9313i sub-modules except the Ethernet PHYs (Port 1 PHY, Port 2 PHY,
and Virtual PHY)
A single-module reset is initiated by assertion of the following:
„ Port 2 PHY Reset - PHY2_RST (bit 2) in the Reset Control Register (RESET_CTL) or Reset (bit
15) in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
- Resets the Port 2 PHY
„ Port 1 PHY Reset - PHY1_RST (bit 1) in the Reset Control Register (RESET_CTL) or Reset (bit
15) in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
- Resets the Port 1 PHY
„ Virtual PHY Reset - VPHY_RST (bit 0) in the Reset Control Register (RESET_CTL) or Reset (bit
15) in the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)
- Resets the Virtual PHY
System Interrupt Controller
The LAN9313/LAN9313i provides a multi-tier programmable interrupt structure which is controlled by
the System Interrupt Controller. At the top level are the Interrupt Status Register (INT_STS) and
Interrupt Enable Register (INT_EN). These registers aggregate and control all interrupts from the
various LAN9313/LAN9313i sub-modules. The LAN9313/LAN9313i is capable of generating interrupt
events from the following:
„ 1588 Time Stamp
„ Switch Fabric
„ Ethernet PHYs
„ GPIOs
„ General Purpose Timer
„ Software (general purpose)
A dedicated programmable IRQ interrupt output pin is provided for external indication of any
LAN9313/LAN9313i interrupts. The IRQ pin is controlled via the Interrupt Configuration Register
(IRQ_CFG), which allows configuration of the IRQ buffer type, polarity, and de-assertion interval.
Revision 1.2 (04-08-08)
20
DATASHEET
SMSC LAN9313/LAN9313i