LAN9313 Datasheet, PDF (41/398 Pages) SMSC Corporation – Three Port 10/100 Managed Ethernet Switch with MII

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
Chapter 4 Clocking, Resets, and Power Management
4.1
4.2
Clocks
The LAN9313/LAN9313i includes a clock module which provides generation of all system clocks as
required by the various sub-modules of the device. The LAN9313/LAN9313i requires a fixed-frequency
25MHz clock source for use by the internal clock oscillator and PLL. This is typically provided by
attaching a 25MHz crystal to the XI and XO pins as specified in Section 14.6, "Clock Circuit," on
page 394. Optionally, this clock can be provided by driving the XI input pin with a single-ended 25MHz
clock source. If a single-ended source is selected, the clock input must run continuously for normal
device operation. The internal PLL generates a fixed 200MHz base clock which is used to derive all
LAN9313/LAN9313i sub-system clocks.
In addition to the sub-system clocks, the clock module is also responsible for generating the clocks
used for the general purpose timer and free-running clock. Refer to Chapter 11, "General Purpose
Timer & Free-Running Clock," on page 141 for additional details.
Note: Crystal specifications are provided in Table 14.10, “LAN9313/LAN9313i Crystal Specifications,”
on page 394.
Resets
The LAN9313/LAN9313i provides multiple hardware and software reset sources, which allow varying
levels of the LAN9313/LAN9313i to be reset. All resets can be categorized into three reset types as
described in the following sections:
„ Chip-Level Resets
—Power-On Reset (POR)
—nRST Pin Reset
„ Multi-Module Resets
—Digital Reset (DIGITAL_RST)
„ Single-Module Resets
—Port 2 PHY Reset
—Port 1 PHY Reset
—Virtual PHY Reset
The LAN9313/LAN9313i supports the use of configuration straps to allow automatic custom
configurations of various LAN9313/LAN9313i parameters. These configuration strap values are set
upon de-assertion of all chip-level resets and can be used to easily set the default parameters of the
chip at power-on or pin (nRST) reset. Refer to Section 4.2.4, "Configuration Straps," on page 45 for
detailed information on the usage of these straps.
Note: The LAN9313/LAN9313i EEPROM Loader is run upon a power-on reset, nRST pin reset, and
digital reset. Refer to Section 8.2.4, "EEPROM Loader," on page 113 for additional information.
Table 4.1 summarizes the effect of the various reset sources on the LAN9313/LAN9313i. Refer to the
following sections for detailed information on each of these reset types.
SMSC LAN9313/LAN9313i
41
DATASHEET
Revision 1.2 (04-08-08)