LAN9313 Datasheet, PDF (246/398 Pages) SMSC Corporation – Three Port 10/100 Managed Ethernet Switch with MII

13.2.2.9
Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)
Index (decimal): 18
Size:
16 bits
This read/write register is used to control the special modes of the Port x PHY.
Note: This register is re-written by the EEPROM Loader following the release of reset or a RELOAD
command. Refer to Section 8.2.4, "EEPROM Loader," on page 113 for more information.
BITS
DESCRIPTION
TYPE
15:8 RESERVED
RO
7:5 PHY Mode (MODE[2:0])
R/W
This field controls the PHY mode of operation. Refer to Table 13.10 for a
NASR
definition of each mode.
Note 13.60
4:0 PHY Address (PHYADD)
R/W
The PHY Address field determines the MMI address to which the PHY will _NASR
respond and is also used for initialization of the cipher (scrambler) key. Each Note 13.60
PHY must have a unique address. Refer to Section 7.1.1, "PHY
Addressing," on page 84 for additional information.
Note:
No check is performed to ensure that this address is unique from
the other PHY addresses (Port 1 PHY, Port 2 PHY, and Virtual
PHY).
DEFAULT
-
Note 13.61
Note 13.62
Note 13.60 Register bits designated as NASR are reset when the Port x PHY Reset is generated via
the Reset Control Register (RESET_CTL). The NASR designation is only applicable when
the Reset (PHY_RST) bit of the Port x PHY Basic Control Register
(PHY_BASIC_CONTROL_x) is set.
Note 13.61 The default value of this field is determined by a combination of the configuration straps
autoneg_strap_x, speed_strap_x, and duplex_strap_x. If the autoneg_strap_x is 1, then
the default MODE[2:0] value is 111b. Else, the default value of this field is determined by
the remaining straps. MODE[2]=0, MODE[1]=(speed_strap_1 for Port 1 PHY,
speed_strap_2 for Port 2 PHY), and MODE[0]=(duplex_strap_1 for Port 1 PHY,
duplex_strap_2 for Port 2 PHY). Configuration strap values are latched upon the de-
assertion of a chip-level reset as described in Section 4.2.4, "Configuration Straps," on
page 45. Refer to Section 4.2.4, "Configuration Straps," on page 45 for configuration strap
definitions.
Note 13.62 The default value of this field is determined by the phy_addr_sel_strap configuration strap.
Refer to Section 7.1.1, "PHY Addressing," on page 84 for additional information.
Table 13.10 MODE[2:0] Definitions
AFFECTED REGISTER BIT VALUES
MODE[2:0]
MODE DEFINITIONS
PHY_BASIC_CONTROL_x
PHY_AN_ADV_x
000
10BASE-T Half Duplex. Auto-negotiation disabled.
001
10BASE-T Full Duplex. Auto-negotiation disabled.
010
100BASE-TX Half Duplex. Auto-negotiation
disabled. CRS is active during Transmit & Receive.
[13,12,10,8]
0000
0001
1000
[8,7,6,5]
N/A
N/A
N/A
Revision 1.2 (04-08-08)
246
DATASHEET
SMSC LAN9313/LAN9313i